x86 cpu: Allow some cpuid functions during romstage
Allow calls to cpu_phys_address_size and its support functions during romstage. This enables the proper display of MTRRs during romstage without duplicating this code. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I6f6465c150a683ce91f1494ebb5d9ac60b75b795 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6bfd517088b6a2e8a5958a837e6c8c471de19fd0 Original-Change-Id: I429f9beb69298836acdd71d17a7bcb717939dfc2 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277392 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10561 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -142,8 +142,12 @@ static inline unsigned int cpuid_edx(unsigned int op)
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#define X86_VENDOR_ANY 0xfe
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#define X86_VENDOR_UNKNOWN 0xff
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int cpu_phys_address_size(void);
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#define CPUID_FEATURE_PAE (1 << 6)
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#define CPUID_FEATURE_PSE36 (1 << 17)
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int cpu_cpuid_extended_level(void);
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int cpu_have_cpuid(void);
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int cpu_phys_address_size(void);
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#ifndef __SIMPLE_DEVICE__
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@ -2,6 +2,7 @@
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ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
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romstage-y += cbfs_and_run.c
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romstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c
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romstage-y += memset.c
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romstage-y += memcpy.c
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romstage-y += memmove.c
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@ -13,6 +14,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y)
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ramstage-y += c_start.S
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ramstage-y += cpu.c
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ramstage-y += cpu_common.c
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ramstage-y += pci_ops_conf1.c
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ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
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ramstage-y += exception.c
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@ -31,12 +31,6 @@ static inline int flag_is_changeable_p(uint32_t flag)
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return ((f1^f2) & flag) != 0;
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}
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/* Probe for the CPUID instruction */
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int cpu_have_cpuid(void)
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{
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
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/*
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* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
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* by the fact that they preserve the flags across the division of 5/2.
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@ -130,26 +124,6 @@ static const char *cpu_vendor_name(int vendor)
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return name;
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}
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static int cpu_cpuid_extended_level(void)
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{
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return cpuid_eax(0x80000000);
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}
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#define CPUID_FEATURE_PAE (1 << 6)
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#define CPUID_FEATURE_PSE36 (1 << 17)
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int cpu_phys_address_size(void)
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{
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if (!(cpu_have_cpuid()))
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return 32;
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if (cpu_cpuid_extended_level() >= 0x80000008)
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return cpuid_eax(0x80000008) & 0xff;
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if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
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return 36;
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return 32;
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}
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static void identify_cpu(struct device *cpu)
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{
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char vendor_name[16];
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@ -0,0 +1,56 @@
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#include <console/console.h>
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#include <cpu/cpu.h>
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#include <arch/io.h>
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#include <string.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/lapic.h>
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#include <arch/cpu.h>
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#include <device/path.h>
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#include <device/device.h>
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#include <smp/spinlock.h>
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(uint32_t flag)
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{
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uint32_t f1, f2;
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asm(
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"pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl\n\t"
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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return ((f1^f2) & flag) != 0;
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}
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/* Probe for the CPUID instruction */
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int cpu_have_cpuid(void)
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{
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
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int cpu_cpuid_extended_level(void)
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{
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return cpuid_eax(0x80000000);
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}
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int cpu_phys_address_size(void)
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{
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if (!(cpu_have_cpuid()))
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return 32;
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if (cpu_cpuid_extended_level() >= 0x80000008)
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return cpuid_eax(0x80000008) & 0xff;
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if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
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return 36;
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return 32;
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}
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