mainboard/google/octopus: configure EC_AP_INT_ODL
Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards that support it. Also removing unnecessary IO standby support since we don't use this pin to wake up the SoC. BRANCH=octopus BUG=b:122552125,b:120679547 TEST=CTS tests with changes Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/30788 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -194,7 +194,9 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */
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PAD_NC(GPIO_134, NONE),/* GPIO_134 -- EC_AP_INT_ODL */
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/* EC_AP_INT_ODL */
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PAD_CFG_GPI_APIC_LOW(GPIO_134, NONE, DEEP),
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/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPIO_135, NONE, DEEP, LEVEL, INVERT),
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PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */
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@ -18,4 +18,7 @@
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#include <baseboard/ec.h>
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/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */
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#define EC_ENABLE_SYNC_IRQ
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#endif
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@ -18,4 +18,7 @@
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#include <baseboard/gpio.h>
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/* EC sync irq is GPP_134_IRQ */
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#define EC_SYNC_IRQ GPIO_134_IRQ
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#endif /* MAINBOARD_GPIO_H */
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@ -195,7 +195,9 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */
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PAD_NC(GPIO_134, NONE),/* GPIO_134 -- unused */
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/* EC_AP_INT_ODL */
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PAD_CFG_GPI_APIC_LOW(GPIO_134, NONE, DEEP),
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PAD_CFG_GPI_IRQ_WAKE(GPIO_135, NONE, DEEP, LEVEL, INVERT),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */
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PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */
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@ -84,4 +84,7 @@
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
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/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */
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#define EC_ENABLE_SYNC_IRQ
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#endif
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@ -39,4 +39,7 @@
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#define MEM_CONFIG2 GPIO_70
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#define MEM_CONFIG3 GPIO_71
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/* EC sync irq is GPP_134_IRQ */
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#define EC_SYNC_IRQ GPIO_134_IRQ
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#endif /* BASEBOARD_GPIO_H */
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@ -22,10 +22,6 @@
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static const struct pad_config default_override_table[] = {
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PAD_NC(GPIO_104, UP_20K),
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/* CAM_SOC_EC_SYNC */
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PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, LEVEL, INVERT, TxDRxE,
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DISPUPD),
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/* EN_PP3300_TOUCHSCREEN */
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PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
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DISPUPD),
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@ -18,7 +18,4 @@
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#include <baseboard/ec.h>
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/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */
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#define EC_ENABLE_SYNC_IRQ
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#endif
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@ -18,7 +18,4 @@
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#include <baseboard/gpio.h>
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/* EC sync irq is GPP_134_IRQ */
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#define EC_SYNC_IRQ GPIO_134_IRQ
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#endif /* MAINBOARD_GPIO_H */
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@ -38,9 +38,6 @@ static const struct pad_config default_override_table[] = {
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/* PCIE_CLKREQ3_B -- unused */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),
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/* CAM_SOC_EC_SYNC */
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PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
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DISPUPD),
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PAD_NC(GPIO_138, UP_20K), /* PEN_PDCT_ODL -- unused */
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PAD_NC(GPIO_139, UP_20K), /* PEN_INT_ODL -- unused */
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@ -28,10 +28,6 @@ static const struct pad_config default_override_table[] = {
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PAD_NC(GPIO_67, UP_20K),
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PAD_NC(GPIO_117, UP_20K),
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/* CAM_SOC_EC_SYNC */
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PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
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DISPUPD),
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PAD_NC(GPIO_138, DN_20K),
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PAD_NC(GPIO_139, DN_20K),
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PAD_NC(GPIO_140, UP_20K),
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@ -21,10 +21,6 @@
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static const struct pad_config default_override_table[] = {
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PAD_NC(GPIO_104, UP_20K),
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/* CAM_SOC_EC_SYNC */
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PAD_CFG_GPI_APIC_IOS(GPIO_134, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE,
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DISPUPD),
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/* EN_PP3300_TOUCHSCREEN */
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PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
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DISPUPD),
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