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sb/intel/bd82x6x/finalize: Use new PMBASE API 

Change-Id: Id42bbea1f2deb0be80af2c8008045d37a926126a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph 2018-06-28 14:13:06 +02:00 committed by Patrick Georgi
parent ecb2399ab8
commit 2dc63895eb
1 changed files with 2 additions and 8 deletions
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10
src/southbridge/intel/bd82x6x/finalize.c
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@ -18,16 +18,13 @@
#include <device/pci_ops.h>
#include <console/post_codes.h>
#include <cpu/x86/smm.h>
#include "pch.h"
#include <southbridge/intel/common/pmbase.h>
#include <spi-generic.h>
#include "chip.h"
#include "pch.h"
void intel_pch_finalize_smm(void)
{
u16 tco1_cnt;
u16 pmbase;
if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) ||
IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) {
/* Copy flash regions from FREG0-4 to PR0-4
@ -72,10 +69,7 @@ void intel_pch_finalize_smm(void)
pci_read_config32(PCI_DEV(0, 27, 0), 0x74));
/* TCO_Lock */
pmbase = smm_get_pmbase();
tco1_cnt = inw(pmbase + TCO1_CNT);
tco1_cnt |= TCO_LOCK;
outw(tco1_cnt, pmbase + TCO1_CNT);
write_pmbase16(TCO1_CNT, read_pmbase16(TCO1_CNT) | TCO_LOCK);
/* Indicate finalize step with post code */
outb(POST_OS_BOOT, 0x80);