soc/intel/cannonlake: Clear PMCON status bits

The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.

BUG=b:128482282
BRANCH=None
TEST=In cbmem logs, check for value of “prev_sleep_state” using command
cbmem –c | grep “prev_sleep_state”

For cold reboot, "prev_sleep_state 5"
For warm reboot, "prev_sleep_state 0"

Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

src/soc/intel/cannonlake/finalize.c

@@ -85,6 +85,8 @@ static void pch_finalize(void)
 	}
 
 	pch_handle_sideband(config);
+
+	pmc_clear_pmcon_sts();
 }
 
 static void soc_finalize(void *unused)

src/soc/intel/cannonlake/include/soc/pm.h

@@ -169,5 +169,8 @@ uint16_t smbus_tco_regs(void);
 /* Set the DISB after DRAM init */
 void pmc_set_disb(void);
 
+/* Clear PMCON status bits */
+void pmc_clear_pmcon_sts(void);
+
 #endif /* !defined(__ACPI__) */
 #endif

src/soc/intel/cannonlake/pmutil.c

@@ -142,6 +142,20 @@ void pmc_set_disb(void)
 	write8(addr, disb_val);
 }
 
+void pmc_clear_pmcon_sts(void)
+{
+	uint32_t reg_val;
+	uint8_t *addr;
+	addr = pmc_mmio_regs();
+
+	reg_val = read32(addr + GEN_PMCON_A);
+	/* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+	 * while retaining MS4V write-1-to-clear bit */
+	reg_val &= ~(MS4V);
+
+	write32((addr + GEN_PMCON_A), reg_val);
+}
+
 /*
  * PMC controller gets hidden from PCI bus
  * during FSP-Silicon init call. Hence PWRMBASE