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mb/google/sarien/variants: Add Thermal Sensors information 

Add available thermal sensors information for CPU throttling action.

BRANCH=None
BUG=b:120058043
TEST=Built and tested on Arcada system

Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Sumeet Pawnikar 2019-01-14 17:56:51 +05:30 committed by Patrick Georgi
parent 72812fa516
commit 2dfa53f80e
2 changed files with 36 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
View File

@ -16,16 +16,24 @@
#define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_PASSIVE 80
#define DPTF_CPU_CRITICAL 100 #define DPTF_CPU_CRITICAL 100
/* Skin Sensor for CPU VR temperature monitor */
#define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "Thermal 1" #define DPTF_TSR0_SENSOR_NAME "Skin"
#define DPTF_TSR0_PASSIVE 55 #define DPTF_TSR0_PASSIVE 55
#define DPTF_TSR0_CRITICAL 80 #define DPTF_TSR0_CRITICAL 70
/* Memory Sensor for DDR temperature monitor */
#define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "Thermal 2" #define DPTF_TSR1_SENSOR_NAME "DDR"
#define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_PASSIVE 55
#define DPTF_TSR1_CRITICAL 80 #define DPTF_TSR1_CRITICAL 80
/* M.2 Sensor for Ambient temperature monitor */
#define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "Ambient"
#define DPTF_TSR2_PASSIVE 55
#define DPTF_TSR2_CRITICAL 70
#undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_FAN_CONTROL
#undef DPTF_ENABLE_CHARGER #undef DPTF_ENABLE_CHARGER
@ -33,8 +41,14 @@ Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */ /* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
/* CPU Effect on Board */ /* CPU Throttle Effect on Skin (TSR0) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
}) })
Name (MPPC, Package () Name (MPPC, Package ()

22
src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl
View File

@ -16,16 +16,24 @@
#define DPTF_CPU_PASSIVE 80 #define DPTF_CPU_PASSIVE 80
#define DPTF_CPU_CRITICAL 100 #define DPTF_CPU_CRITICAL 100
/* Skin Sensor for CPU VR temperature monitor */
#define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "Thermal 1" #define DPTF_TSR0_SENSOR_NAME "Skin"
#define DPTF_TSR0_PASSIVE 55 #define DPTF_TSR0_PASSIVE 55
#define DPTF_TSR0_CRITICAL 80 #define DPTF_TSR0_CRITICAL 70
/* Memory Sensor for DDR temperature monitor */
#define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "Thermal 2" #define DPTF_TSR1_SENSOR_NAME "DDR"
#define DPTF_TSR1_PASSIVE 55 #define DPTF_TSR1_PASSIVE 55
#define DPTF_TSR1_CRITICAL 80 #define DPTF_TSR1_CRITICAL 80
/* M.2 Sensor for Ambient temperature monitor */
#define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "Ambient"
#define DPTF_TSR2_PASSIVE 55
#define DPTF_TSR2_CRITICAL 70
#undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_FAN_CONTROL
#undef DPTF_ENABLE_CHARGER #undef DPTF_ENABLE_CHARGER
@ -33,8 +41,14 @@ Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */ /* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
/* CPU Effect on Board */ /* CPU Throttle Effect on Skin (TSR0) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
}) })
Name (MPPC, Package () Name (MPPC, Package ()