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src/vendorcode/amd: correct spelling of MTRR 

Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/4806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Paul Menzel 2014-01-25 15:59:31 +01:00 committed by Martin Roth
parent f8532b16be
commit 2e0d9447db
40 changed files with 69 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c
View File

@ -120,7 +120,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTTR region
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -151,7 +151,7 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTTR enable bit and turn off modification bit
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData &= 0xFFFFFFFFFFF7FFFFull;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);

12
src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
View File

@ -208,7 +208,7 @@ AllocateExecutionCache (
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, StdHeader);
// Setup MTTRs for region 0 to region 2
// Setup MTRRs for region 0 to region 2
VariableMttrBase = AMD_MTRR_VARIABLE_BASE6;
for (i = 0; i < 3; i++) {
// Exit if no more cache available
@ -265,7 +265,7 @@ AllocateExecutionCache (
if (StartAddr < 0x100000) {
// Region below 1MB
// Fixed MTTR region
// Fixed MTRR region
if ((StartAddr + ExeCacheSize) > 0xFFFFF) {
ExeCacheSize = 0xFFFFF - StartAddr;
AgesaStatus = AGESA_WARNING;
@ -276,7 +276,7 @@ AllocateExecutionCache (
i, StartAddr, ExeCacheSize, 0, StdHeader);
}
// Find start and end of MTTR
// Find start and end of MTRR
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((StartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + (((StartAddr + ExeCacheSize) >> 15) & 0x7);
@ -290,14 +290,14 @@ AllocateExecutionCache (
}
}
// Setup MTTRs
// Setup MTRRs
MsrData = WP_IO;
for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) {
LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader);
}
} else {
// Region above 1MB
// Variable MTTR region
// Variable MTRR region
if (VariableMttrBase > AMD_MTRR_VARIABLE_BASE7) {
AgesaStatus = AGESA_ERROR;
AgesaInfo = AGESA_THREE_CACHE_REGIONS_ABOVE_1MB;
@ -373,7 +373,7 @@ AllocateExecutionCache (
}
}
// Turn on MTTR enable bit and turn off modification bit
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData &= 0xFFFFFFFFFFF7FFFFull;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);

2
src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm
View File

@ -147,7 +147,7 @@ EFLoop:
.endw
.endif
; restore variable MTTR6 and MTTR7 to default states
; restore variable MTRR6 and MTRR7 to default states
mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6
xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
xor edx, edx

2
src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c
View File

@ -156,7 +156,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList)
__writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData);
}
// restore variable MTTR6 and MTTR7 to default states
// restore variable MTRR6 and MTRR7 to default states
for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared
__writemsr (msrno, 0);

2
src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c
View File

@ -153,7 +153,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
// Enable variable MTTRs
// Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);

6
src/vendorcode/amd/agesa/f10/cpcarmac.inc
View File

@ -187,7 +187,7 @@ SetupDramMap:
inc cl
.endw
; setup MTTR for stacks
; setup MTRR for stacks
mov ebx, WB_DRAM_TYPE
.if (di == 0) ;core 0
.if (si > 3) ; node 0 to 3 located at 40000h, node 4 to 7 located at 50000h
@ -198,7 +198,7 @@ SetupDramMap:
or edx, ebx
_WRMSR
.else ;core 1 to core 7 start at 60000h
.if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTTR
.if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTRR
shl ebx, 16
.if (si > 1)
shl ebx, 8
@ -207,7 +207,7 @@ SetupDramMap:
_RDMSR
or edx, ebx
_WRMSR
.else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTTR
.else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTRR
mov ecx, AMD_MTRR_FIX16k_80000
_RDMSR
.if (si < 6) ; node 4 and node 5

2
src/vendorcode/amd/agesa/f10/gcccar.inc
View File

@ -1353,7 +1353,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
# setup MTTRs for stacks
# setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.

6
src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c
View File

@ -137,7 +137,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTTR region
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -168,14 +168,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTTR enable bit and turn off modification bit
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFFull;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
// Variable MTTR region
// Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader);

6
src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c
View File

@ -281,7 +281,7 @@ AllocateExecutionCache (
RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
if (RequestStartAddr < 0x100000) {
// Region starts below 1MB - Fixed MTTR region,
// Region starts below 1MB - Fixed MTRR region,
// turn on modification bit: MtrrFixDramModEn
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -299,7 +299,7 @@ AllocateExecutionCache (
i, RequestStartAddr, RequestSize, 0, StdHeader);
}
// Find start MTTR and end MTTR for the requested region
// Find start MTRR and end MTRR for the requested region
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
@ -325,7 +325,7 @@ AllocateExecutionCache (
} else {
// Region above 1MB - Variable MTTR region
// Region above 1MB - Variable MTRR region
// Need to check both VarMTRRs for each requested region for match or overlap
//

2
src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c
View File

@ -148,7 +148,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList)
__writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData);
}
// restore variable MTTR6 and MTTR7 to default states
// restore variable MTRR6 and MTRR7 to default states
for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared
__writemsr (msrno, 0);

2
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c
View File

@ -188,7 +188,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
// Enable variable MTTRs
// Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);

2
src/vendorcode/amd/agesa/f12/cpcarmac.inc
View File

@ -220,7 +220,7 @@ AMD_ENABLE_STACK MACRO
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
; setup MTTRs for stacks
; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.

2
src/vendorcode/amd/agesa/f12/gcccar.inc
View File

@ -1347,7 +1347,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
# setup MTTRs for stacks
# setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.

6
src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
View File

@ -140,7 +140,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTTR region
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -171,14 +171,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTTR enable bit and turn off modification bit
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
// Variable MTTR region
// Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);

6
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c
View File

@ -280,7 +280,7 @@ AllocateExecutionCache (
RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
if (RequestStartAddr < 0x100000) {
// Region starts below 1MB - Fixed MTTR region,
// Region starts below 1MB - Fixed MTRR region,
// turn on modification bit: MtrrFixDramModEn
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -298,7 +298,7 @@ AllocateExecutionCache (
i, RequestStartAddr, RequestSize, 0, StdHeader);
}
// Find start MTTR and end MTTR for the requested region
// Find start MTRR and end MTRR for the requested region
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
@ -324,7 +324,7 @@ AllocateExecutionCache (
} else {
// Region above 1MB - Variable MTTR region
// Region above 1MB - Variable MTRR region
// Need to check both VarMTRRs for each requested region for match or overlap
//

2
src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm
View File

@ -173,7 +173,7 @@ EFLoop:
.endw
.endif
; restore variable MTTR6 and MTTR7 to default states
; restore variable MTRR6 and MTRR7 to default states
mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6
xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
xor edx, edx

2
src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S
View File

@ -157,7 +157,7 @@ EFLoop:
jmp 5b /* .endw */
4: /* .endif */
/* restore variable MTTR6 and MTTR7 to default states */
/* restore variable MTRR6 and MTRR7 to default states */
movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */
xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */
xor %edx, %edx

2
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
View File

@ -192,7 +192,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
// Enable variable MTTRs
// Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);

2
src/vendorcode/amd/agesa/f14/cpcarmac.inc
View File

@ -215,7 +215,7 @@ AMD_ENABLE_STACK MACRO
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
; setup MTTRs for stacks
; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.

2
src/vendorcode/amd/agesa/f14/gcccar.inc
View File

@ -1365,7 +1365,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
# setup MTTRs for stacks
# setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.

6
src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
View File

@ -138,7 +138,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTTR region
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -169,14 +169,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTTR enable bit and turn off modification bit
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
// Variable MTTR region
// Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);

6
src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c
View File

@ -282,7 +282,7 @@ AllocateExecutionCache (
RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
if (RequestStartAddr < 0x100000) {
// Region starts below 1MB - Fixed MTTR region,
// Region starts below 1MB - Fixed MTRR region,
// turn on modification bit: MtrrFixDramModEn
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -300,7 +300,7 @@ AllocateExecutionCache (
i, RequestStartAddr, RequestSize, 0, StdHeader);
}
// Find start MTTR and end MTTR for the requested region
// Find start MTRR and end MTRR for the requested region
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
@ -326,7 +326,7 @@ AllocateExecutionCache (
} else {
// Region above 1MB - Variable MTTR region
// Region above 1MB - Variable MTRR region
// Need to check both VarMTRRs for each requested region for match or overlap
//

2
src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S
View File

@ -187,7 +187,7 @@ EFLoop:
AMD_DISABLE_STACK_FAMILY_HOOK
/* restore variable MTTR6 and MTTR7 to default states */
/* restore variable MTRR6 and MTRR7 to default states */
bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */
jz 6f
movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */

2
src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c
View File

@ -189,7 +189,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
// Enable variable MTTRs
// Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);

2
src/vendorcode/amd/agesa/f15/cpcarmac.inc
View File

@ -221,7 +221,7 @@ AMD_ENABLE_STACK MACRO
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
; setup MTTRs for stacks
; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.

2
src/vendorcode/amd/agesa/f15/gcccar.inc
View File

@ -1368,7 +1368,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
# setup MTTRs for stacks
# setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.

6
src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c
View File

@ -137,7 +137,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTTR region
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -168,14 +168,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTTR enable bit and turn off modification bit
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
// Variable MTTR region
// Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);

6
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c
View File

@ -281,7 +281,7 @@ AllocateExecutionCache (
RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
if (RequestStartAddr < 0x100000) {
// Region starts below 1MB - Fixed MTTR region,
// Region starts below 1MB - Fixed MTRR region,
// turn on modification bit: MtrrFixDramModEn
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -299,7 +299,7 @@ AllocateExecutionCache (
i, RequestStartAddr, RequestSize, 0, StdHeader);
}
// Find start MTTR and end MTTR for the requested region
// Find start MTRR and end MTRR for the requested region
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
@ -325,7 +325,7 @@ AllocateExecutionCache (
} else {
// Region above 1MB - Variable MTTR region
// Region above 1MB - Variable MTRR region
// Need to check both VarMTRRs for each requested region for match or overlap
//

2
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S
View File

@ -187,7 +187,7 @@ EFLoop:
AMD_DISABLE_STACK_FAMILY_HOOK
/* restore variable MTTR6 and MTTR7 to default states */
/* restore variable MTRR6 and MTRR7 to default states */
bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */
jz 6f
movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */

2
src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c
View File

@ -188,7 +188,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
// Enable variable MTTRs
// Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);

2
src/vendorcode/amd/agesa/f15tn/cpcarmac.inc
View File

@ -221,7 +221,7 @@ AMD_ENABLE_STACK MACRO
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
; setup MTTRs for stacks
; setup MTRRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.

2
src/vendorcode/amd/agesa/f15tn/gcccar.inc
View File

@ -1677,7 +1677,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
# setup MTTRs for stacks
# setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.

4
src/vendorcode/amd/agesa/f16kb/Include/Filecode.h
View File

@ -575,7 +575,7 @@
#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588)
#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589)
#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A)
#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B)
#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C)
#define PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE (0XF58B)
#define PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE (0XF58C)
#endif // _FILECODE_H_

6
src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c
View File

@ -141,7 +141,7 @@ CopyHeapToTempRamAtPost (
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTTR region
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -172,14 +172,14 @@ CopyHeapToTempRamAtPost (
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTTR enable bit and turn off modification bit
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
// Variable MTTR region
// Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);

6
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c
View File

@ -281,7 +281,7 @@ AllocateExecutionCache (
RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
if (RequestStartAddr < 0x100000) {
// Region starts below 1MB - Fixed MTTR region,
// Region starts below 1MB - Fixed MTRR region,
// turn on modification bit: MtrrFixDramModEn
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
@ -299,7 +299,7 @@ AllocateExecutionCache (
i, RequestStartAddr, RequestSize, 0, StdHeader);
}
// Find start MTTR and end MTTR for the requested region
// Find start MTRR and end MTRR for the requested region
StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
@ -325,7 +325,7 @@ AllocateExecutionCache (
} else {
// Region above 1MB - Variable MTTR region
// Region above 1MB - Variable MTRR region
// Need to check both VarMTRRs for each requested region for match or overlap
//

2
src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S
View File

@ -179,7 +179,7 @@ EFLoop:
AMD_DISABLE_STACK_FAMILY_HOOK
/* restore variable MTTR6 and MTTR7 to default states */
/* restore variable MTRR6 and MTRR7 to default states */
bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */
jz 6f
movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */

2
src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c
View File

@ -191,7 +191,7 @@ HeapManagerInit (
MsrData = (UINT64) (AMD_TEMP_TOM);
LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
// Enable variable MTTRs
// Enable variable MTRRs
LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);

2
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c
View File

@ -64,7 +64,7 @@
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE
#define FILECODE PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*

2
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
View File

@ -70,7 +70,7 @@
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE
#define FILECODE PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*

2
src/vendorcode/amd/agesa/f16kb/gcccar.inc
View File

@ -1042,7 +1042,7 @@ SetupStack:
mov $TOP_MEM2, %ecx # MSR:C001_001D
_WRMSR
# setup MTTRs for stacks
# setup MTRRs for stacks
# A speculative read can be generated by a speculative fetch mis-aligned in a code zone
# or due to a data zone being interpreted as code. When a speculative read occurs outside a
# controlled region (intentionally used by software), it could cause an unwanted cache eviction.