mb/emulation/qemu-q35: Split smm_close() and smm_lock()
Change-Id: I6d8efe783e6cc5413c3fd0583574a075a2c3876b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -36,7 +36,8 @@ struct ied_header {
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/* These helpers are for performing SMM relocation. */
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void northbridge_write_smram(u8 smram);
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void smm_open_aseg(void);
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void smm_close(void);
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void smm_open(void);
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void smm_lock(void);
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void smm_relocate(void);
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@ -18,8 +18,7 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
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if (CONFIG(SMM_ASEG))
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smm_open_aseg();
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smm_open();
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/* FIXME: on X86_64 the save state size is smaller than the size of the SMM stub */
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*smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
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@ -77,6 +76,9 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase,
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static void post_mp_init(void)
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{
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/* Limit access to SMRAM to SMM module. */
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smm_close();
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/* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */
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global_smi_enable();
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@ -78,6 +78,26 @@ void smm_region(uintptr_t *start, size_t *size)
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printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB);
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}
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void smm_open(void)
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{
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/* Set D_OPEN */
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if (CONFIG(SMM_ASEG))
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pci_write_config8(HOST_BRIDGE, SMRAMC, D_OPEN | G_SMRAME | C_BASE_SEG);
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if (CONFIG(SMM_TSEG))
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pci_and_config8(HOST_BRIDGE, ESMRAMC, ~T_EN);
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}
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void smm_close(void)
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{
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/* Clear D_OPEN */
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if (CONFIG(SMM_ASEG))
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pci_write_config8(HOST_BRIDGE, SMRAMC, G_SMRAME | C_BASE_SEG);
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if (CONFIG(SMM_TSEG))
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pci_or_config8(HOST_BRIDGE, ESMRAMC, T_EN);
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}
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void smm_lock(void)
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{
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/*
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@ -87,13 +107,5 @@ void smm_lock(void)
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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if (CONFIG(SMM_TSEG))
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pci_or_config8(HOST_BRIDGE, ESMRAMC, T_EN);
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pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG);
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}
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void smm_open_aseg(void)
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{
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pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, G_SMRAME | C_BASE_SEG | D_OPEN);
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pci_write_config8(HOST_BRIDGE, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG);
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}
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