mb/google/nissa/var/xivu: Update overridetree
Update override devicetree based on schematics. BUG=b:236576117 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2986ae6fd1f51efc6b9bb18ff2b7186357e55fcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Ian Feng
Felix Held
parent
fe5ad028a4
commit
2e1bcd3985
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@ -253,3 +253,6 @@ config BOARD_GOOGLE_PUJJO
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config BOARD_GOOGLE_XIVU
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bool "-> Xivu"
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GENESYSLOGIC_GL9750
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@ -1,6 +1,217 @@
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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# SOC Aux orientation override:
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# This is a bitfield that corresponds to up to 4 TCSS ports.
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# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
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# TcssAuxOri = 0101b
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# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
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# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
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# motherboard to USBC connector
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register "tcss_aux_ori" = "5"
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
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register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C1 | Touchscreen |
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#| I2C2 | |
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#| I2C3 | Audio |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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device domain 0 on
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device ref i2c1 on
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chip drivers/i2c/hid
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register "generic.hid" = ""ELAN9008""
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register "generic.desc" = ""ELAN Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "generic.reset_delay_ms" = "300"
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register "generic.reset_off_delay_ms" = "1"
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register "generic.enable_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "generic.enable_delay_ms" = "6"
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register "generic.stop_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
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register "generic.stop_off_delay_ms" = "1"
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register "generic.has_power_resource" = "1"
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register "generic.disable_gpio_export_in_crs" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 10 on end
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end
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chip drivers/generic/gpio_keys
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register "name" = ""PENH""
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register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
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register "key.wake_gpe" = "GPE0_DW2_15"
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register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
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register "key.wakeup_event_action" = "EV_ACT_ANY"
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register "key.dev_name" = ""EJCT""
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register "key.linux_code" = "SW_PEN_INSERTED"
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register "key.linux_input_type" = "EV_SW"
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register "key.label" = ""pen_eject""
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device generic 0 on
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end
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end
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end
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device ref i2c3 on
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chip drivers/i2c/generic
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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chip drivers/generic/alc1015
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register "hid" = ""RTL1019""
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register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
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device generic 0 on end
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end
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end
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device ref i2c5 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
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register "wake" = "GPE0_DW2_14"
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register "probed" = "1"
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device i2c 15 on end
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end
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end
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device ref pcie_rp4 on
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# PCIe 4 WLAN
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register "pch_pcie_rp[PCH_RP(4)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip drivers/wifi/generic
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register "wake" = "GPE0_DW1_03"
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device pci 00.0 on end
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end
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
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register "srcclk_pin" = "2"
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device generic 0 on end
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end
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end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use tcss_usb3_port2 as usb3_port
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device generic 1 alias conn1 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port2 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A1 (DB)""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
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device ref usb2_port4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Camera""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port8 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A0 (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A1 (DB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
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device ref usb3_port2 on end
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end
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end
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end
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end
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end
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end
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