From 2e25ac6afe84d9535fa6d89b847915e96f5d266b Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 3 Jul 2020 12:06:04 +0200
Subject: [PATCH] haswell: relocate `romstage_common` to northbridge

Other platforms do this as well. It will ease refactoring on follow-ups.

Change-Id: I643982a58c6f5370c78acef93740f27df001a06d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
---
 src/cpu/intel/haswell/Makefile.inc                |  1 -
 src/cpu/intel/haswell/haswell.h                   | 10 ----------
 src/northbridge/intel/haswell/Makefile.inc        |  1 +
 src/northbridge/intel/haswell/haswell.h           | 10 ++++++++++
 src/{cpu => northbridge}/intel/haswell/romstage.c |  2 +-
 5 files changed, 12 insertions(+), 12 deletions(-)
 rename src/{cpu => northbridge}/intel/haswell/romstage.c (97%)

diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index aebeed497a..b93b911aeb 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -1,5 +1,4 @@
 ramstage-y += haswell_init.c
-romstage-y += romstage.c
 romstage-y += ../car/romstage.c
 
 ramstage-y += acpi.c
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 7906b8355b..b336e4c2c6 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -118,16 +118,6 @@
 # error "CONFIG_IED_REGION_SIZE is not a power of 2"
 #endif
 
-struct pei_data;
-struct rcba_config_instruction;
-struct romstage_params {
-	struct pei_data *pei_data;
-	const void *gpio_map;
-	const struct rcba_config_instruction *rcba_config;
-	void (*copy_spd)(struct pei_data *);
-};
-void romstage_common(const struct romstage_params *params);
-
 /* Lock MSRs */
 void intel_cpu_haswell_finalize_smm(void);
 
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 8ef3079f51..b2fd5307bf 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -14,6 +14,7 @@ ramstage-y += minihd.c
 
 romstage-y += memmap.c
 romstage-y += raminit.c
+romstage-y += romstage.c
 romstage-y += early_init.c
 romstage-y += report_platform.c
 
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index c3930493da..b98d88085e 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -189,6 +189,16 @@
 
 void intel_northbridge_haswell_finalize_smm(void);
 
+struct pei_data;
+struct rcba_config_instruction;
+struct romstage_params {
+	struct pei_data *pei_data;
+	const void *gpio_map;
+	const struct rcba_config_instruction *rcba_config;
+	void (*copy_spd)(struct pei_data *peid);
+};
+void romstage_common(const struct romstage_params *params);
+
 void haswell_early_initialization(void);
 void haswell_late_initialization(void);
 void set_translation_table(int start, int end, u64 base, int inc);
diff --git a/src/cpu/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
similarity index 97%
rename from src/cpu/intel/haswell/romstage.c
rename to src/northbridge/intel/haswell/romstage.c
index 7886de07ed..579eca791b 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -7,11 +7,11 @@
 #include <cbmem.h>
 #include <commonlib/helpers.h>
 #include <romstage_handoff.h>
+#include <cpu/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <southbridge/intel/lynxpoint/me.h>
-#include "haswell.h"
 
 void romstage_common(const struct romstage_params *params)
 {