mb/google/fizz/variants/karma: Clear GPP_B4 when entering S5
Set GPP_B4 to low in S5 to meet touch panel power sequence BUG=b:124197348 BRANCH=master TEST=Verify GPP_B4 is low. Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12 Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -17,6 +17,7 @@
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#include <ec/google/chromeec/smm.h>
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#include <soc/smm.h>
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#include <baseboard/variants.h>
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#include <variant/ec.h>
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void mainboard_smi_espi_handler(void)
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@ -24,8 +25,11 @@ void mainboard_smi_espi_handler(void)
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chromeec_smi_process_events();
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}
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void __weak variant_smi_sleep(u8 slp_typ) {}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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variant_smi_sleep(slp_typ);
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chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
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MAINBOARD_EC_S5_WAKE_EVENTS);
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}
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@ -29,6 +29,8 @@ const struct pad_config *variant_early_gpio_table(size_t *num);
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const struct cros_gpio *variant_cros_gpios(size_t *num);
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void variant_smi_sleep(u8 slp_typ);
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struct nhlt;
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void variant_nhlt_init(struct nhlt *nhlt);
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void variant_nhlt_oem_overrides(const char **oem_id, const char **oem_table_id,
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@ -2,3 +2,5 @@ bootblock-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += nhlt.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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@ -0,0 +1,28 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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#define TS_ENABLE GPP_B4
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void variant_smi_sleep(u8 slp_typ)
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{
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if (slp_typ == ACPI_S5) {
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/* Set TS to disable */
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gpio_set(TS_ENABLE, 0);
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}
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}
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