nb/intel/haswell: Use new fixed BAR accessors
There are some cases in `northbridge_topology_init` where condensing the operation using one macro changes the binary, and have been left as-is. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I59c7d1f8d816b95e86d39dcbf7bc7ce8c34f0770 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51865 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
Nico Huber
parent
936536cd2b
commit
2e397aebad
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@ -20,16 +20,16 @@ unsigned long acpi_fill_mcfg(unsigned long current)
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static unsigned long acpi_fill_dmar(unsigned long current)
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{
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struct device *const igfx_dev = pcidev_on_root(2, 0);
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const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
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const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
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const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
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const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
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const u32 gfxvtbar = mchbar_read32(GFXVTBAR) & ~0xfff;
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const u32 vtvc0bar = mchbar_read32(VTVC0BAR) & ~0xfff;
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const bool gfxvten = mchbar_read32(GFXVTBAR) & 0x1;
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const bool vtvc0en = mchbar_read32(VTVC0BAR) & 0x1;
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/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
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const bool emit_igd =
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igfx_dev && igfx_dev->enabled &&
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gfxvtbar && gfxvten &&
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!MCHBAR32(GFXVTBAR + 4);
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!mchbar_read32(GFXVTBAR + 4);
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/* First, add DRHD entries */
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if (emit_igd) {
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@ -42,7 +42,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
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}
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/* VTVC0BAR has to be set, enabled, and in 32-bit space */
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if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
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if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) {
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const unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
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@ -138,17 +138,17 @@ static void haswell_setup_misc(void)
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u32 reg32;
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/* Erratum workarounds */
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reg32 = MCHBAR32(SAPMCTL);
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reg32 = mchbar_read32(SAPMCTL);
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reg32 |= (1 << 9) | (1 << 10);
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MCHBAR32(SAPMCTL) = reg32;
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mchbar_write32(SAPMCTL, reg32);
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/* Enable SA Clock Gating */
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reg32 = MCHBAR32(SAPMCTL);
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MCHBAR32(SAPMCTL) = reg32 | 1;
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reg32 = mchbar_read32(SAPMCTL);
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mchbar_write32(SAPMCTL, reg32 | 1);
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reg32 = MCHBAR32(INTRDIRCTL);
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reg32 = mchbar_read32(INTRDIRCTL);
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reg32 |= (1 << 4) | (1 << 5);
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MCHBAR32(INTRDIRCTL) = reg32;
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mchbar_write32(INTRDIRCTL, reg32);
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}
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static void haswell_setup_iommu(void)
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@ -159,10 +159,10 @@ static void haswell_setup_iommu(void)
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return;
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/* Setup BARs: zeroize top 32 bits; set enable bit */
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MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32;
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MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1;
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MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32;
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MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1;
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mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
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mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
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mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
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mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
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/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
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u32 reg32;
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@ -66,7 +66,7 @@ static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len)
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*/
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static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len)
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{
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u32 bar = MCHBAR32(index);
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u32 bar = mchbar_read32(index);
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/* If not enabled don't report it */
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if (!(bar & 0x1))
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@ -399,16 +399,16 @@ static void disable_devices(void)
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static void init_egress(void)
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{
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/* VC0: Enable, ID0, TC0 */
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EPBAR32(EPVC0RCTL) = (1 << 31) | (0 << 24) | (1 << 0);
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epbar_write32(EPVC0RCTL, 1 << 31 | 0 << 24 | 1 << 0);
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/* No Low Priority Extended VCs, one Extended VC */
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EPBAR32(EPPVCCAP1) = (0 << 4) | (1 << 0);
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epbar_write32(EPPVCCAP1, 0 << 4 | 1 << 0);
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/* VC1: Enable, ID1, TC1 */
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EPBAR32(EPVC1RCTL) = (1 << 31) | (1 << 24) | (1 << 1);
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epbar_write32(EPVC1RCTL, 1 << 31 | 1 << 24 | 1 << 1);
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/* Poll the VC1 Negotiation Pending bit */
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while ((EPBAR16(EPVC1RSTS) & (1 << 1)) != 0)
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while ((epbar_read16(EPVC1RSTS) & (1 << 1)) != 0)
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;
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}
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@ -416,39 +416,24 @@ static void northbridge_dmi_init(void)
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{
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const bool is_haswell_h = !CONFIG(INTEL_LYNXPOINT_LP);
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u16 reg16;
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u32 reg32;
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/* Steps prior to DMI ASPM */
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if (is_haswell_h) {
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/* Configure DMI De-Emphasis */
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reg16 = DMIBAR16(DMILCTL2);
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reg16 |= (1 << 6); /* 0b: -6.0 dB, 1b: -3.5 dB */
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DMIBAR16(DMILCTL2) = reg16;
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dmibar_setbits16(DMILCTL2, 1 << 6); /* 0b: -6.0 dB, 1b: -3.5 dB */
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reg32 = DMIBAR32(DMIL0SLAT);
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reg32 |= (1 << 31);
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DMIBAR32(DMIL0SLAT) = reg32;
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dmibar_setbits32(DMIL0SLAT, 1 << 31);
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dmibar_setbits32(DMILLTC, 1 << 29);
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reg32 = DMIBAR32(DMILLTC);
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reg32 |= (1 << 29);
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DMIBAR32(DMILLTC) = reg32;
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reg32 = DMIBAR32(DMI_AFE_PM_TMR);
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reg32 &= ~0x1f;
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reg32 |= 0x13;
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DMIBAR32(DMI_AFE_PM_TMR) = reg32;
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dmibar_clrsetbits32(DMI_AFE_PM_TMR, 0x1f, 0x13);
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}
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/* Clear error status bits */
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DMIBAR32(DMIUESTS) = 0xffffffff;
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DMIBAR32(DMICESTS) = 0xffffffff;
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dmibar_write32(DMIUESTS, 0xffffffff);
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dmibar_write32(DMICESTS, 0xffffffff);
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if (is_haswell_h) {
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/* Enable ASPM L0s and L1 on SA link, should happen before PCH link */
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reg16 = DMIBAR16(DMILCTL);
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reg16 |= (1 << 1) | (1 << 0);
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DMIBAR16(DMILCTL) = reg16;
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dmibar_setbits16(DMILCTL, 1 << 1 | 1 << 0);
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}
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}
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@ -460,17 +445,14 @@ static void northbridge_topology_init(void)
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u32 reg32;
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/* Set the CID1 Egress Port 0 Root Topology */
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reg32 = EPBAR32(EPESD);
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reg32 &= ~(0xff << 16);
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reg32 |= 1 << 16;
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EPBAR32(EPESD) = reg32;
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epbar_clrsetbits32(EPESD, 0xff << 16, 1 << 16);
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reg32 = EPBAR32(EPLE1D);
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reg32 = epbar_read32(EPLE1D);
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reg32 &= ~(0xff << 16);
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reg32 |= 1 | (1 << 16);
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EPBAR32(EPLE1D) = reg32;
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EPBAR32(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE;
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EPBAR32(EPLE1A + 4) = 0;
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epbar_write32(EPLE1D, reg32);
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epbar_write32(EPLE1A, CONFIG_FIXED_DMIBAR_MMIO_BASE);
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epbar_write32(EPLE1A + 4, 0);
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for (unsigned int i = 0; i <= 2; i++) {
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const struct device *const dev = pcidev_on_root(1, i);
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@ -478,13 +460,13 @@ static void northbridge_topology_init(void)
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if (!dev || !dev->enabled)
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continue;
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EPBAR32(eple_a[i]) = (u32)PCI_DEV(0, 1, i);
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EPBAR32(eple_a[i] + 4) = 0;
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epbar_write32(eple_a[i], (u32)PCI_DEV(0, 1, i));
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epbar_write32(eple_a[i] + 4, 0);
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reg32 = EPBAR32(eple_d[i]);
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reg32 = epbar_read32(eple_d[i]);
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reg32 &= ~(0xff << 16);
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reg32 |= 1 | (1 << 16);
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EPBAR32(eple_d[i]) = reg32;
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epbar_write32(eple_d[i], reg32);
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pci_update_config32(dev, PEG_ESD, ~(0xff << 16), (1 << 16));
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pci_write_config32(dev, PEG_LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE);
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@ -496,43 +478,35 @@ static void northbridge_topology_init(void)
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}
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/* Set the CID1 DMI Port Root Topology */
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reg32 = DMIBAR32(DMIESD);
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reg32 &= ~(0xff << 16);
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reg32 |= 1 << 16;
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DMIBAR32(DMIESD) = reg32;
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dmibar_clrsetbits32(DMIESD, 0xff << 16, 1 << 16);
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reg32 = DMIBAR32(DMILE1D);
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reg32 = dmibar_read32(DMILE1D);
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reg32 &= ~(0xffff << 16);
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reg32 |= 1 | (2 << 16);
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DMIBAR32(DMILE1D) = reg32;
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DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE;
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DMIBAR32(DMILE1A + 4) = 0;
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dmibar_write32(DMILE1D, reg32);
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dmibar_write32(DMILE1A, CONFIG_FIXED_RCBA_MMIO_BASE);
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dmibar_write32(DMILE1A + 4, 0);
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DMIBAR32(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE;
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DMIBAR32(DMILE2A + 4) = 0;
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reg32 = DMIBAR32(DMILE2D);
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dmibar_write32(DMILE2A, CONFIG_FIXED_EPBAR_MMIO_BASE);
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dmibar_write32(DMILE2A + 4, 0);
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reg32 = dmibar_read32(DMILE2D);
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reg32 &= ~(0xff << 16);
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reg32 |= 1 | (1 << 16);
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DMIBAR32(DMILE2D) = reg32;
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dmibar_write32(DMILE2D, reg32);
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/* Program RO and Write-Once Registers */
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DMIBAR32(DMIPVCCAP1) = DMIBAR32(DMIPVCCAP1);
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DMIBAR32(DMILCAP) = DMIBAR32(DMILCAP);
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dmibar_setbits32(DMIPVCCAP1, 0);
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dmibar_setbits32(DMILCAP, 0);
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}
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static void northbridge_init(struct device *dev)
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{
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u8 bios_reset_cpl, pair;
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init_egress();
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northbridge_dmi_init();
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northbridge_topology_init();
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/* Enable Power Aware Interrupt Routing. */
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pair = MCHBAR8(INTRDIRCTL);
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pair &= ~0x7; /* Clear 2:0 */
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pair |= 0x4; /* Fixed Priority */
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MCHBAR8(INTRDIRCTL) = pair;
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mchbar_clrsetbits8(INTRDIRCTL, 0x7, 0x4); /* Clear 2:0, set Fixed Priority */
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disable_devices();
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@ -540,9 +514,7 @@ static void northbridge_init(struct device *dev)
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* Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU
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* that BIOS has initialized memory and power management.
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*/
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bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
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bios_reset_cpl |= 3;
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MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
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mchbar_setbits8(BIOS_RESET_CPL, 3);
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printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
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/* Configure turbo power limits 1ms after reset complete bit. */
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@ -565,21 +537,21 @@ static void northbridge_final(struct device *dev)
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pci_or_config32(dev, TOLUD, 1 << 0);
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/* Memory Controller Lockdown */
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MCHBAR32(MC_LOCK) |= 0x8f;
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mchbar_setbits32(MC_LOCK, 0x8f);
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MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */
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MCHBAR32_OR(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */
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MCHBAR32_OR(DMIVCLIM, 1 << 31);
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MCHBAR32_OR(CRDTLCK, 1 << 0);
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MCHBAR32_OR(MCARBLCK, 1 << 0);
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MCHBAR32_OR(REQLIM, 1 << 31);
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MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */
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MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */
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mchbar_setbits32(MMIO_PAVP_MSG, 1 << 0); /* PAVP */
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mchbar_setbits32(PCU_DDR_PTM_CTL, 1 << 5); /* DDR PTM */
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mchbar_setbits32(DMIVCLIM, 1 << 31);
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mchbar_setbits32(CRDTLCK, 1 << 0);
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mchbar_setbits32(MCARBLCK, 1 << 0);
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mchbar_setbits32(REQLIM, 1 << 31);
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mchbar_setbits32(UMAGFXCTL, 1 << 0); /* UMA GFX */
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mchbar_setbits32(VTDTRKLCK, 1 << 0); /* VTDTRK */
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/* Read+write the following */
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MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM);
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MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP);
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MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID);
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mchbar_setbits32(VDMBDFBARKVM, 0);
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mchbar_setbits32(VDMBDFBARPAVP, 0);
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mchbar_setbits32(HDAUDRID, 0);
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}
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static struct device_operations mc_ops = {
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@ -70,10 +70,10 @@ static void report_memory_config(void)
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{
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int i;
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const u32 addr_decoder_common = MCHBAR32(MAD_CHNL);
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const u32 addr_decoder_common = mchbar_read32(MAD_CHNL);
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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(MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
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(mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
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printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
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(addr_decoder_common >> 0) & 3,
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@ -81,7 +81,7 @@ static void report_memory_config(void)
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < NUM_CHANNELS; i++) {
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const u32 ch_conf = MCHBAR32(MAD_DIMM(i));
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const u32 ch_conf = mchbar_read32(MAD_DIMM(i));
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printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
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printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
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@ -164,7 +164,7 @@ static void sdram_initialize(struct pei_data *pei_data)
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}
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/* Print the MRC version after executing the UEFI PEI stage */
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u32 version = MCHBAR32(MRC_REVISION);
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u32 version = mchbar_read32(MRC_REVISION);
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printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n",
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(version >> 24) & 0xff, (version >> 16) & 0xff,
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(version >> 8) & 0xff, (version >> 0) & 0xff);
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@ -234,10 +234,10 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
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memset(mem_info, 0, sizeof(struct memory_info));
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const u32 ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
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const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
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for (ch = 0; ch < NUM_CHANNELS; ch++) {
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const u32 ch_conf = MCHBAR32(MAD_DIMM(ch));
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const u32 ch_conf = mchbar_read32(MAD_DIMM(ch));
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/* DIMMs A/B */
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for (d_num = 0; d_num < NUM_SLOTS; d_num++) {
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const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256;
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