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cpu/x86/smm: Drop SMI handler address from struct 

Change-Id: Ib925b11ba269e0f3a9a0a7550705bf2a6794c5b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2019-08-05 12:49:09 +03:00
parent 544369ebf3
commit 2e3aff8d86
6 changed files with 6 additions and 15 deletions
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2
src/soc/intel/cannonlake/include/soc/smm.h
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@ -29,8 +29,6 @@ struct ied_header {
} __packed; } __packed;
struct smm_relocation_params { struct smm_relocation_params {
uintptr_t smram_base;
size_t smram_size;
uintptr_t ied_base; uintptr_t ied_base;
size_t ied_size; size_t ied_size;
msr_t smrr_base; msr_t smrr_base;

5
src/soc/intel/cannonlake/smmrelocate.c
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@ -188,7 +188,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
phys_bits = cpu_phys_address_size(); phys_bits = cpu_phys_address_size();
smm_region(&tseg_base, &tseg_size); smm_region(&tseg_base, &tseg_size);
smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */ /* SMRR has 32-bits of valid address aligned to 4KiB. */
@ -248,11 +247,11 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
fill_in_relocation_params(&smm_reloc_params); fill_in_relocation_params(&smm_reloc_params);
smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
if (smm_reloc_params.ied_size) if (smm_reloc_params.ied_size)
setup_ied_area(&smm_reloc_params); setup_ied_area(&smm_reloc_params);
*perm_smbase = smm_reloc_params.smram_base;
*perm_smsize = smm_reloc_params.smram_size;
*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
} }

2
src/soc/intel/icelake/include/soc/smm.h
View File

@ -28,8 +28,6 @@ struct ied_header {
} __packed; } __packed;
struct smm_relocation_params { struct smm_relocation_params {
uintptr_t smram_base;
size_t smram_size;
uintptr_t ied_base; uintptr_t ied_base;
size_t ied_size; size_t ied_size;
msr_t smrr_base; msr_t smrr_base;

5
src/soc/intel/icelake/smmrelocate.c
View File

@ -187,7 +187,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
phys_bits = cpu_phys_address_size(); phys_bits = cpu_phys_address_size();
smm_region(&tseg_base, &tseg_size); smm_region(&tseg_base, &tseg_size);
smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */ /* SMRR has 32-bits of valid address aligned to 4KiB. */
@ -247,11 +246,11 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
fill_in_relocation_params(&smm_reloc_params); fill_in_relocation_params(&smm_reloc_params);
smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
if (smm_reloc_params.ied_size) if (smm_reloc_params.ied_size)
setup_ied_area(&smm_reloc_params); setup_ied_area(&smm_reloc_params);
*perm_smbase = smm_reloc_params.smram_base;
*perm_smsize = smm_reloc_params.smram_size;
*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
} }

2
src/soc/intel/skylake/include/soc/smm.h
View File

@ -30,8 +30,6 @@ struct ied_header {
} __packed; } __packed;
struct smm_relocation_params { struct smm_relocation_params {
uintptr_t smram_base;
size_t smram_size;
uintptr_t ied_base; uintptr_t ied_base;
size_t ied_size; size_t ied_size;
msr_t smrr_base; msr_t smrr_base;

5
src/soc/intel/skylake/smmrelocate.c
View File

@ -197,7 +197,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
phys_bits = cpuid_eax(0x80000008) & 0xff; phys_bits = cpuid_eax(0x80000008) & 0xff;
smm_region(&tseg_base, &tseg_size); smm_region(&tseg_base, &tseg_size);
smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */ /* SMRR has 32-bits of valid address aligned to 4KiB. */
@ -257,11 +256,11 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
fill_in_relocation_params(&smm_reloc_params); fill_in_relocation_params(&smm_reloc_params);
smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
if (smm_reloc_params.ied_size) if (smm_reloc_params.ied_size)
setup_ied_area(&smm_reloc_params); setup_ied_area(&smm_reloc_params);
*perm_smbase = smm_reloc_params.smram_base;
*perm_smsize = smm_reloc_params.smram_size;
*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
} }