diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 36c79eb5d1..d14a809f66 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -31,11 +31,7 @@
 #define DEFAULT_GPIOBASE	0x0480
 #define DEFAULT_PMBASE		0x0500
 
-#ifndef __ACPI__
-#define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA		0xfed1c000
-#endif
+#include <southbridge/intel/common/rcba.h>
 
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
@@ -194,10 +190,6 @@ int southbridge_detect_s3_resume(void);
 /* Root Complex Register Block */
 #define RCBA		0xf0
 
-#define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + (x))))
-#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x))))
-#define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + (x))))
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index 38dfa385ad..b70c7f8885 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -25,11 +25,8 @@
 #endif
 
 #define DEFAULT_TBAR		((u8 *)0xfed1b000)
-#ifndef __ACPI__
-#define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA		0xfed1c000
-#endif
+
+#include <southbridge/intel/common/rcba.h>
 
 #if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35)
 /*
@@ -154,10 +151,6 @@
 #define SMB_SMI_EN		(1 << 1)
 #define HST_EN			(1 << 0)
 
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
 #define RCBA_V0CTL		0x0014
 #define RCBA_V1CAP		0x001c
 #define RCBA_V1CTL		0x0020
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 88e0ad01f3..5aa41dd6c6 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -25,11 +25,8 @@
 #endif
 
 #define DEFAULT_TBAR		((u8 *)0xfed1b000)
-#ifndef __ACPI__
-#define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA		0xfed1c000
-#endif
+
+#include <southbridge/intel/common/rcba.h>
 
 #define DEFAULT_PMBASE		0x00000500
 #define DEFAULT_TCOBASE		(DEFAULT_PMBASE + 0x60)
@@ -147,10 +144,6 @@
 #define SMB_SMI_EN		(1 << 1)
 #define HST_EN			(1 << 0)
 
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
 #define RCBA_V0CTL		0x0014
 #define RCBA_V1CAP		0x001c
 #define RCBA_V1CTL		0x0020