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src/drivers: Add required space before opening parenthesis '(' 

Change-Id: I4d0087b2557862d04be54cf42f01b3223cb723ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16321
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-08-25 20:50:50 +02:00 committed by Martin Roth
parent d75b04f2b3
commit 2e4d80687d
8 changed files with 21 additions and 21 deletions
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4
src/drivers/ati/ragexl/xlinit.c
View File

@ -528,7 +528,7 @@ static void ati_ragexl_init(struct device *dev)
res = dev->resource_list;
if(res->flags & IORESOURCE_IO) {
if (res->flags & IORESOURCE_IO) {
res = res->next;
}
@ -542,7 +542,7 @@ static void ati_ragexl_init(struct device *dev)
/* Fix this to look for the correct index. */
//if (dev->resource_list && dev->resource_list->next)
res = dev->resource_list->next->next;
if(res->flags & IORESOURCE_MEM) {
if (res->flags & IORESOURCE_MEM) {
info->ati_regbase = res2mmio(res, 0x400, 0); //using auxiliary register
}

2
src/drivers/intel/fsp1_0/fsp_util.c
View File

@ -303,7 +303,7 @@ static void find_fsp_hob_update_mrc(void *unused)
print_hob_type_structure(0x000, FspHobListPtr);
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
if(save_mrc_data(FspHobListPtr))
if (save_mrc_data(FspHobListPtr))
update_mrc_cache(NULL);
else
printk(BIOS_DEBUG,"Not updating MRC data in flash.\n");

2
src/drivers/intel/fsp1_1/ramstage.c
View File

@ -143,7 +143,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
/* Mark graphics init done after SiliconInit if VBT was provided */
#if IS_ENABLED(CONFIG_GOP_SUPPORT)
/* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs
* to be #if'd out instead of using if(). */
* to be #if'd out instead of using if (). */
if (silicon_init_params.GraphicsConfigPtr)
gfx_set_init_done(1);
#endif

6
src/drivers/intel/gma/intel_dp.c
View File

@ -642,7 +642,7 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
(unsigned long)gtt_read(PCH_PP_STATUS),
(unsigned long)gtt_read(PCH_PP_CONTROL));
for(i = 0, status = gtt_read(PCH_PP_STATUS); ((status & mask) != value) && (i < 5000);
for (i = 0, status = gtt_read(PCH_PP_STATUS); ((status & mask) != value) && (i < 5000);
status = gtt_read(PCH_PP_STATUS)){
udelay(10);
}
@ -972,7 +972,7 @@ intel_dp_get_link_status(struct intel_dp *intel_dp,
DP_LINK_STATUS_SIZE);
printk(BIOS_SPEW, "%s:", __func__);
for(i = 0; i < /* !!sizeof(link_status) == 4*/
for (i = 0; i < /* !!sizeof(link_status) == 4*/
DP_LINK_STATUS_SIZE; i++)
printk(BIOS_SPEW, " %02x", link_status[i]);
printk(BIOS_SPEW, "\n");
@ -1308,7 +1308,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
gtt_write(DP_TP_CTL(port), temp);
for(i = 0; i < 10; i++){
for (i = 0; i < 10; i++){
u32 status;
status = gtt_read(DP_TP_STATUS(port));
if (status & DP_TP_STATUS_IDLE_DONE)

8
src/drivers/ipmi/ipmi_kcs.c
View File

@ -55,7 +55,7 @@ static int wait_ibf_timeout(int port)
if (!(ipmi_kcs_status(port) & IPMI_KCS_IBF))
return 0;
udelay(100);
} while(timeout--);
} while (timeout--);
printk(BIOS_ERR, "wait_ibf timeout!\n");
return timeout;
}
@ -67,7 +67,7 @@ static int wait_obf_timeout(int port)
if ((ipmi_kcs_status(port) & IPMI_KCS_OBF))
return 0;
udelay(100);
} while(timeout--);
} while (timeout--);
printk(BIOS_ERR, "wait_obf timeout!\n");
return timeout;
@ -160,7 +160,7 @@ static int ipmi_kcs_send_message(int port, int netfn, int lun, int cmd,
return ret;
}
while(len-- > 1) {
while (len-- > 1) {
if ((ret = ipmi_kcs_send_data_byte(port, *msg++))) {
printk(BIOS_ERR, "IPMI BYTE WRITE failed\n");
return ret;
@ -189,7 +189,7 @@ static int ipmi_kcs_read_message(int port, unsigned char *msg, int len)
if (wait_ibf_timeout(port))
return 1;
for(;;) {
for (;;) {
status = ipmi_kcs_status(port);
if (IPMI_KCS_STATE(status) == IPMI_KCS_STATE_IDLE)

2
src/drivers/net/ne2k.c
View File

@ -153,7 +153,7 @@ unsigned long compute_ip_checksum_from_sram(unsigned short offset, unsigned shor
* compute an ip style checksum.
*/
sum = 0;
for(i = 0; i < length; i++) {
for (i = 0; i < length; i++) {
unsigned long v;
v = eth_pio_read_byte((TX_START << 8)+i+offset, eth_nic_base);
if (i & 1) {

6
src/drivers/uart/uart8250mem.c
View File

@ -62,7 +62,7 @@ static int uart8250_mem_can_tx_byte(void *base)
static void uart8250_mem_tx_byte(void *base, unsigned char data)
{
unsigned long int i = SINGLE_CHAR_TIMEOUT;
while(i-- && !uart8250_mem_can_tx_byte(base))
while (i-- && !uart8250_mem_can_tx_byte(base))
udelay(1);
uart8250_write(base, UART8250_TBR, data);
}
@ -70,7 +70,7 @@ static void uart8250_mem_tx_byte(void *base, unsigned char data)
static void uart8250_mem_tx_flush(void *base)
{
unsigned long int i = FIFO_TIMEOUT;
while(i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT))
while (i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT))
udelay(1);
}
@ -82,7 +82,7 @@ static int uart8250_mem_can_rx_byte(void *base)
static unsigned char uart8250_mem_rx_byte(void *base)
{
unsigned long int i = SINGLE_CHAR_TIMEOUT;
while(i-- && !uart8250_mem_can_rx_byte(base))
while (i-- && !uart8250_mem_can_rx_byte(base))
udelay(1);
if (i)
return uart8250_read(base, UART8250_RBR);

12
src/drivers/usb/ehci_debug.c
View File

@ -39,8 +39,8 @@ static int dbgp_enabled(void);
# define dprintk(LEVEL, args...) \
do { if (!dbgp_enabled()) printk(LEVEL, ##args); } while (0)
#else
# define dbgp_print_data(x) do {} while(0)
# define dprintk(LEVEL, args...) do {} while(0)
# define dbgp_print_data(x) do {} while (0)
# define dprintk(LEVEL, args...) do {} while (0)
#endif
#define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f))
@ -460,8 +460,8 @@ try_next_port:
dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc);
}
if(port_map_tried && (new_debug_port != debug_port)) {
if(--playtimes) {
if (port_map_tried && (new_debug_port != debug_port)) {
if (--playtimes) {
ehci_debug_select_port(debug_port);
goto try_next_time;
}
@ -495,7 +495,7 @@ try_next_port:
cmd = read32(&ehci_regs->command);
} while ((cmd & CMD_RESET) && (--loop > 0));
if(!loop) {
if (!loop) {
dprintk(BIOS_INFO, "Could not reset EHCI controller.\n");
// on some systems it works without succeeding here.
// return -2;
@ -525,7 +525,7 @@ try_next_port:
status = read32(&ehci_regs->status);
} while ((status & STS_HALT) && (--loop > 0));
if(!loop) {
if (!loop) {
dprintk(BIOS_INFO, "EHCI could not be started.\n");
return -3;
}