From 2e5e99c48ce374e8ad1d92a77e54c5e22a770f0b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 12 Jul 2020 23:06:47 +0200 Subject: [PATCH] sb/intel/i82801dx: Declare reset register in FADT According to Intel Document 290744 (ICH4 datasheet), 0xcf9 is the reset register, and setting bits 1 and 2 will result in a hard reset. Change-Id: Id1a532857d9643d222d61c3902faadd471ae2a9a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43384 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/i82801dx/fadt.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index cdab3f44c1..319e6a6f88 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -52,16 +52,16 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; - fadt->reset_reg.space_id = 0; - fadt->reset_reg.bit_width = 0; + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.access_size = 0; - fadt->reset_reg.addrl = 0x0; - fadt->reset_reg.addrh = 0x0; - - fadt->reset_value = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 0x06; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32;