Drop i855pm port and rename i855gme to i855 instead.

This patch also changes the digitallogic/adl855pc to use that port.
It probably won't work, but at least we will get an error if something
breaks compilation of the i855 code that is there.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/digitallogic/adl855pc/Kconfig

@@ -2,7 +2,7 @@ config BOARD_DIGITALLOGIC_ADL855PC
 	bool "smartModule855"
 	select ARCH_X86
 	select CPU_INTEL_SOCKET_MPGA479M
-	select NORTHBRIDGE_INTEL_I855PM
+	select NORTHBRIDGE_INTEL_I855
 	select SOUTHBRIDGE_INTEL_I82801DBM
 	select SUPERIO_WINBOND_W83627HF
 	select ROMCC

src/mainboard/digitallogic/adl855pc/devicetree.cb

@@ -1,4 +1,4 @@
-chip northbridge/intel/i855pm
+chip northbridge/intel/i855
 	device pci_domain 0 on 
 		device pci 0.0 on end
 		device pci 1.0 on end

src/mainboard/digitallogic/adl855pc/romstage.c

@@ -17,7 +17,7 @@
 #include "arch/i386/lib/console.c"
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c"
-#include "northbridge/intel/i855pm/raminit.h"
+#include "northbridge/intel/i855/raminit.h"
 
 #if 0
 #include "cpu/p6/apic_timer.c"
@@ -25,7 +25,7 @@
 #endif
 
 #include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/i855pm/debug.c"
+#include "northbridge/intel/i855/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c" 
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
@@ -57,8 +57,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i855pm/raminit.c"
+#include "northbridge/intel/i855/raminit.c"
-#include "northbridge/intel/i855pm/reset_test.c"
+#include "northbridge/intel/i855/reset_test.c"
 #include "lib/generic_sdram.c"
 
 static void main(unsigned long bist)

src/northbridge/intel/Kconfig

@@ -6,6 +6,5 @@ source src/northbridge/intel/i440bx/Kconfig
 source src/northbridge/intel/i440lx/Kconfig
 source src/northbridge/intel/i82810/Kconfig
 source src/northbridge/intel/i82830/Kconfig
-source src/northbridge/intel/i855gme/Kconfig
+source src/northbridge/intel/i855/Kconfig
-source src/northbridge/intel/i855pm/Kconfig
 source src/northbridge/intel/i945/Kconfig

src/northbridge/intel/Makefile.inc

@@ -6,6 +6,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440BX) += i440bx
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440LX) += i440lx
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855GME) += i855gme
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855PM) += i855pm
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945

src/northbridge/intel/i855/Kconfig

@@ -1,4 +1,4 @@
-config NORTHBRIDGE_INTEL_I855PM
+config NORTHBRIDGE_INTEL_I855
 	bool
 	select HAVE_HIGH_TABLES
 

src/northbridge/intel/i855/chip.h

@@ -18,8 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-struct northbridge_intel_i855gme_config
+struct northbridge_intel_i855_config
 {
 };
 
-extern struct chip_operations northbridge_intel_i855gme_ops;
+extern struct chip_operations northbridge_intel_i855_ops;

src/northbridge/intel/i855/northbridge.c

@@ -177,7 +177,7 @@ static void enable_dev(struct device *dev)
         }
 }
 
-struct chip_operations northbridge_intel_i855gme_ops = {
+struct chip_operations northbridge_intel_i855_ops = {
-        CHIP_NAME("Intel 855GME Northbridge")
+        CHIP_NAME("Intel 855 Northbridge")
 	.enable_dev = enable_dev,
 };

src/northbridge/intel/i855gme/Kconfig

@@ -1,4 +0,0 @@
-config NORTHBRIDGE_INTEL_I855GME
-	bool
-	select HAVE_HIGH_TABLES
-

src/northbridge/intel/i855pm/Makefile.inc

@@ -1 +0,0 @@
-obj-y += northbridge.o

src/northbridge/intel/i855pm/chip.h

@@ -1,5 +0,0 @@
-struct northbridge_intel_i855pm_config
-{
-};
-
-extern struct chip_operations northbridge_intel_i855pm_ops;

src/northbridge/intel/i855pm/debug.c

@@ -1,164 +0,0 @@
-/*
- * generic K8 debug code, used by mainboard specific romstage.c
- *
- */
-#if 1
-static void print_debug_pci_dev(unsigned dev)
-{
-	print_debug("PCI: ");
-	print_debug_hex8((dev >> 16) & 0xff);
-	print_debug_char(':');
-	print_debug_hex8((dev >> 11) & 0x1f);
-	print_debug_char('.');
-	print_debug_hex8((dev >> 8) & 7);
-}
-
-static void print_pci_devices(void)
-{
-	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
-		dev += PCI_DEV(0,0,1)) {
-		uint32_t id;
-		id = pci_read_config32(dev, PCI_VENDOR_ID);
-		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0x0000)) {
-			continue;
-		}
-		print_debug_pci_dev(dev);
-		print_debug("\r\n");
-	}
-}
-
-static void dump_pci_device(unsigned dev)
-{
-	int i;
-	print_debug_pci_dev(dev);
-	print_debug("\r\n");
-	
-	for(i = 0; i <= 255; i++) {
-		unsigned char val;
-		if ((i & 0x0f) == 0) {
-			print_debug_hex8(i);
-			print_debug_char(':');
-		}
-		val = pci_read_config8(dev, i);
-		print_debug_char(' ');
-		print_debug_hex8(val);
-		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
-		}
-	}
-}
-
-static void dump_pci_devices(void)
-{
-	device_t dev;
-	for(dev = PCI_DEV(0, 0, 0); 
-		dev <= PCI_DEV(0, 0x1f, 0x7); 
-		dev += PCI_DEV(0,0,1)) {
-		uint32_t id;
-		id = pci_read_config32(dev, PCI_VENDOR_ID);
-		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0xffff) ||
-			(((id >> 16) & 0xffff) == 0x0000)) {
-			continue;
-		}
-		dump_pci_device(dev);
-	}
-}
-
-static void dump_spd_registers(const struct mem_controller *ctrl)
-{
-	int i;
-	print_debug("\r\n");
-	for(i = 0; i < 4; i++) {
-		unsigned device;
-		device = ctrl->channel0[i];
-		if (device) {
-			int j;
-			print_debug("dimm: "); 
-			print_debug_hex8(i); 
-			print_debug(".0: ");
-			print_debug_hex8(device);
-			for(j = 0; j < 256; j++) {
-				int status;
-				unsigned char byte;
-				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
-					print_debug_hex8(j);
-					print_debug(": ");
-				}
-				status = smbus_read_byte(device, j);
-				if (status < 0) {
-					print_debug("bad device\r\n");
-					break;
-				}
-				byte = status & 0xff;
-				print_debug_hex8(byte);
-				print_debug_char(' ');
-			}
-			print_debug("\r\n");
-		}
-#if 0
-		device = ctrl->channel1[i];
-		if (device) {
-			int j;
-			print_debug("dimm: "); 
-			print_debug_hex8(i); 
-			print_debug(".1: ");
-			print_debug_hex8(device);
-			for(j = 0; j < 256; j++) {
-				int status;
-				unsigned char byte;
-				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
-					print_debug_hex8(j);
-					print_debug(": ");
-				}
-				status = smbus_read_byte(device, j);
-				if (status < 0) {
-					print_debug("bad device\r\n");
-					break;
-				}
-				byte = status & 0xff;
-				print_debug_hex8(byte);
-				print_debug_char(' ');
-			}
-			print_debug("\r\n");
-		}
-#endif
-	}
-}
-static void dump_smbus_registers(void)
-{
-        int i;
-        print_debug("\r\n");
-        for(i = 1; i < 0x80; i++) {
-                unsigned device;
-                device = i;
-                int j;
-                print_debug("smbus: ");
-                print_debug_hex8(device);
-                for(j = 0; j < 256; j++) {
-                	int status; 
-                        unsigned char byte;
-                        if ((j & 0xf) == 0) {
-                	        print_debug("\r\n");
-                                print_debug_hex8(j);
-                                print_debug(": ");
-                        }
-                        status = smbus_read_byte(device, j);
-                        if (status < 0) {
-                                print_debug("bad device\r\n");
-                                break;
-                        }
-                        byte = status & 0xff;
-                        print_debug_hex8(byte);
-                        print_debug_char(' ');
-                }
-                print_debug("\r\n");
-	}	
-}
-#endif

src/northbridge/intel/i855pm/northbridge.c

@@ -1,151 +0,0 @@
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/cpu.h>
-#include <stdlib.h>
-#include <string.h>
-#include <bitops.h>
-#include "chip.h"
-
-static void ram_resource(device_t dev, unsigned long index,
-        unsigned long basek, unsigned long sizek)
-{
-        struct resource *resource;
-
-        if (!sizek) {
-                return;
-        }
-        resource = new_resource(dev, index);
-        resource->base  = ((resource_t)basek) << 10;
-        resource->size  = ((resource_t)sizek) << 10;
-        resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
-                IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
-{
-	struct resource **best_p = gp;
-	struct resource *best;
-	best = *best_p;
-	if (!best || (best->base > new->base)) {
-		best = new;
-	}
-	*best_p = best;
-}
-
-static uint32_t find_pci_tolm(struct bus *bus)
-{
-	struct resource *min;
-	uint32_t tolm;
-	min = 0;
-	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
-	tolm = 0xffffffffUL;
-	if (min && tolm > min->base) {
-		tolm = min->base;
-	}
-	return tolm;
-}
-
-#if CONFIG_WRITE_HIGH_TABLES==1
-#define HIGH_TABLES_SIZE 64	// maximum size of high tables in KB
-extern uint64_t high_tables_base, high_tables_size;
-#endif
-
-static void pci_domain_set_resources(device_t dev)
-{
-	device_t mc_dev;
-        uint32_t pci_tolm;
-
-        pci_tolm = find_pci_tolm(&dev->link[0]);
-	mc_dev = dev->link[0].children;
-	if (mc_dev) {
-		/* Figure out which areas are/should be occupied by RAM.
-		 * This is all computed in kilobytes and converted to/from
-		 * the memory controller right at the edges.
-		 * Having different variables in different units is
-		 * too confusing to get right.  Kilobytes are good up to
-		 * 4 Terabytes of RAM...
-		 */
-		uint16_t tolm_r;
-		unsigned long tomk, tolmk;
-		int idx;
-
-		/* Get the value of the highest DRB. This tells the end of
-		 * the physical memory.  The units are ticks of 32MB
-		 * i.e. 1 means 32MB.
-		 */
-		tomk = ((unsigned long)pci_read_config8(mc_dev, 0x63)) << 15;
-		/* Compute the top of Low memory */
-		tolmk = pci_tolm >> 10;
-		if (tolmk >= tomk) {
-			/* The PCI hole does does not overlap the memory.
-			 */
-			tolmk = tomk;
-		}
-		/* Write the ram configuration registers,
-		 * preserving the reserved bits.
-		 */
-		tolm_r = pci_read_config16(mc_dev, 0xc4);
-		tolm_r = ((tolmk >> 10) << 3) | (tolm_r & 0xf);
-		pci_write_config16(mc_dev, 0xc4, tolm_r);
-
-		/* Report the memory regions */
-		idx = 10;
-		ram_resource(dev, idx++, 0, 640);
-		ram_resource(dev, idx++, 768, tolmk - 768);
-
-#if CONFIG_WRITE_HIGH_TABLES==1
-		/* Leave some space for ACPI, PIRQ and MP tables */
-		high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
-		high_tables_size = HIGH_TABLES_SIZE * 1024;
-#endif
-	}
-	assign_resources(&dev->link[0]);
-}
-
-static struct device_operations pci_domain_ops = {
-        .read_resources   = pci_domain_read_resources,
-        .set_resources    = pci_domain_set_resources,
-        .enable_resources = enable_childrens_resources,
-        .init             = 0,
-        .scan_bus         = pci_domain_scan_bus,
-};  
-
-static void cpu_bus_init(device_t dev)
-{
-        initialize_cpus(&dev->link[0]);
-}
-
-static void cpu_bus_noop(device_t dev)
-{
-}
-
-static struct device_operations cpu_bus_ops = {
-        .read_resources   = cpu_bus_noop,
-        .set_resources    = cpu_bus_noop,
-        .enable_resources = cpu_bus_noop,
-        .init             = cpu_bus_init,
-        .scan_bus         = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
-        struct device_path path;
-
-        /* Set the operations if it is a special bus type */
-        if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
-                dev->ops = &pci_domain_ops;
-		pci_set_method(dev);
-        }
-        else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
-                dev->ops = &cpu_bus_ops;
-        }
-}
-
-struct chip_operations northbridge_intel_i855pm_ops = {
-        CHIP_NAME("Intel 855PM Northbridge")
-	.enable_dev = enable_dev,
-};

src/northbridge/intel/i855pm/raminit.h

@@ -1,12 +0,0 @@
-#ifndef RAMINIT_H
-#define RAMINIT_H
-
-/* I think the 855 is only four sockets -- RGM */
-#define DIMM_SOCKETS 4
-struct mem_controller {
-  device_t d0;
-  uint16_t channel0[DIMM_SOCKETS];
-};
-
-
-#endif /* RAMINIT_H */

src/northbridge/intel/i855pm/reset_test.c

@@ -1,19 +0,0 @@
-/* Convert to C by yhlu */
-/* converted to 855 by RGM */
-#define MCH_DRC 0x70
-#define DRC_DONE (1 << 29)
-	/* If I have already booted once skip a bunch of initialization */
-	/* To see if I have already booted I check to see if memory
-	 * has been enabled.
-	 */
-static int bios_reset_detected(void) {
-	uint32_t dword;
-	
-	dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
-	
-	if( (dword & DRC_DONE) != 0 ) {
-		return 1;
-	} 
-	
-	return 0;
-}