mb/google/link: Remove Link's own native graphics init
The code was already orphaned since its hook-up was removed
with a6be58fece (nb/intel/sandybridge: Remove the C native
graphic init).
Change-Id: Ia554c457e2f3a2dc42965ac5cded0be8e82311fb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Nico Huber
parent
ec93be5208
commit
2e6c3c8936
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@ -14,8 +14,6 @@ config BOARD_SPECIFIC_OPTIONS
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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select SERIRQ_CONTINUOUS_MODE
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
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select MAINBOARD_HAS_LIBGFXINIT
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select HAVE_IFD_BIN
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select HAVE_ME_BIN
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@ -17,9 +17,6 @@ ramstage-y += ec.c
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romstage-y += chromeos.c
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ramstage-y += chromeos.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
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@ -1,374 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <string.h>
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#include <stdlib.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <delay.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/interrupt.h>
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#include <boot/coreboot_tables.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <northbridge/intel/sandybridge/gma.h>
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#include <device/pci.h>
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#include <ec/google/chromeec/ec.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <edid.h>
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#include "ec.h"
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#include "onboard.h"
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#include "i915io.h"
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enum {
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vmsg = 1, vio = 2, vspin = 4,
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};
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static int verbose = 0;
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static unsigned int *mmio;
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static unsigned int graphics;
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static unsigned short addrport;
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static unsigned short dataport;
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static unsigned int physbase;
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static u32 htotal, hblank, hsync, vtotal, vblank, vsync;
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const u32 link_edid_data[] = {
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0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000,
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0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259,
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0x00545017, 0x01010000, 0x01010101, 0x01010101,
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0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031,
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0xb510003a, 0x19000010, 0x00000000, 0x00000000,
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0x00000000, 0x00000000, 0x00000000, 0x4c00fe00,
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0x69442047, 0x616c7073, 0x20200a79, 0xfe000000,
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0x31504c00, 0x45513932, 0x50532d31, 0x24003141,
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};
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#define READ32(addr) io_i915_READ32(addr)
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#define WRITE32(val, addr) io_i915_WRITE32(val, addr)
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static char *regname(unsigned long addr)
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{
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static char name[16];
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snprintf(name, sizeof(name), "0x%lx", addr);
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return name;
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}
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unsigned long io_i915_READ32(unsigned long addr)
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{
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unsigned long val;
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outl(addr, addrport);
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val = inl(dataport);
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if (verbose & vio)
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printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val);
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return val;
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}
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void io_i915_WRITE32(unsigned long val, unsigned long addr)
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{
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if (verbose & vio)
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printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val);
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outl(addr, addrport);
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outl(val, dataport);
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}
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/*
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2560
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4 words per
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4 *p
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10240
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4k bytes per page
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4096/p
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2.50
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1700 lines
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1700 * p
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4250.00
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PTEs
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*/
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static void
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setgtt(int start, int end, unsigned long base, int inc)
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{
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int i;
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for(i = start; i < end; i++){
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u32 word = base + i*inc;
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WRITE32(word|1,(i*4)|1);
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}
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}
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static unsigned long tickspermicrosecond = 1795;
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static unsigned long long globalstart;
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static unsigned long
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microseconds(unsigned long long start, unsigned long long end)
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{
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unsigned long ret;
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ret = ((end - start)/tickspermicrosecond);
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return ret;
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}
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static unsigned long globalmicroseconds(void)
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{
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return microseconds(globalstart, rdtscll());
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}
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extern struct iodef iodefs[];
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extern int niodefs;
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static int i915_init_done = 0;
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/* fill the palette. This runs when the P opcode is hit. */
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/* and, yes, it's needed for even 32 bits per pixel */
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static void palette(void)
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{
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int i;
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unsigned long color = 0;
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for(i = 0; i < 256; i++, color += 0x010101){
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io_i915_WRITE32(color, _LGC_PALETTE_A + (i << 2));
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}
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}
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static unsigned long times[4096];
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static int run(int index)
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{
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int i, prev = 0;
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struct iodef *id, *lastidread = NULL;
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unsigned long u, t;
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if (index >= niodefs)
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return index;
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/* state machine! */
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for(i = index, id = &iodefs[i]; id->op; i++, id++){
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switch (id->op) {
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case M:
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if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n",
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globalmicroseconds(), id->msg);
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break;
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case P:
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palette();
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break;
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case R:
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u = READ32(id->addr);
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if (verbose & vio)
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printk(BIOS_SPEW, "\texpect %08lx\n", id->data);
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/* we're looking for something. */
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if (lastidread->addr == id->addr){
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/* they're going to be polling.
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* just do it 1000 times
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*/
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for (t = 0; t < 1000 && id->data != u; t++){
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u = READ32(id->addr);
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}
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if (verbose & vspin) printk(BIOS_SPEW,
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"%s: # loops %ld got %08lx want %08lx\n",
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regname(id->addr),
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t, u, id->data);
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}
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lastidread = id;
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break;
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case W:
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WRITE32(id->data, id->addr);
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if (id->addr == PCH_PP_CONTROL){
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if (verbose & vio)
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printk(BIOS_SPEW, "PCH_PP_CONTROL\n");
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switch (id->data & 0xf) {
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case 8: break;
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case 7: break;
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default: udelay(100000);
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if (verbose & vio)
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printk(BIOS_SPEW, "U %d\n", 100000);
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}
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}
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break;
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case V:
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if (id->count < 8){
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prev = verbose;
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verbose = id->count;
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} else {
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verbose = prev;
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}
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printk(BIOS_SPEW, "Change verbosity to %d\n", verbose);
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break;
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case I:
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printk(BIOS_SPEW, "run: return %d\n", i+1);
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return i+1;
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break;
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default:
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printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i);
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return -1;
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}
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if (id->udelay)
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udelay(id->udelay);
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if (i < ARRAY_SIZE(times))
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times[i] = globalmicroseconds();
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}
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printk(BIOS_SPEW, "run: return %d\n", i);
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return i+1;
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}
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int i915lightup_sandy(const struct i915_gpu_controller_info *info,
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u32 pphysbase, u16 piobase, u8 *pmmio, u32 pgfx)
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{
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static struct edid edid;
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const struct edid_mode *mode;
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int edid_ok;
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int index;
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u32 auxin[16], auxout[16];
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mmio = (void *)pmmio;
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addrport = piobase;
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dataport = addrport + 4;
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physbase = pphysbase;
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graphics = pgfx;
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printk(BIOS_SPEW, "i915lightup: graphics %p mmio %p"
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"addrport %04x physbase %08x\n",
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(void *)graphics, mmio, addrport, physbase);
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globalstart = rdtscll();
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edid_ok = decode_edid((unsigned char *)&link_edid_data,
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sizeof(link_edid_data), &edid);
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mode = &edid.mode;
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printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
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edid.framebuffer_bits_per_pixel = 32;
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htotal = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16);
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printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal);
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hblank = (mode->ha - 1) | ((mode->ha + mode->hbl - 1) << 16);
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printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank);
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hsync = (mode->ha + mode->hso - 1) |
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((mode->ha + mode->hso + mode->hspw - 1) << 16);
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printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync);
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vtotal = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16);
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printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal);
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vblank = (mode->va - 1) | ((mode->va + mode->vbl - 1) << 16);
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printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank);
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vsync = (mode->va + mode->vso - 1) |
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((mode->va + mode->vso + mode->vspw - 1) << 16);
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printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync);
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printk(BIOS_SPEW, "Table has %d elements\n", niodefs);
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index = run(0);
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printk(BIOS_SPEW, "Run returns %d\n", index);
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auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe;
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14);
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auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0;
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0);
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index = run(index);
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printk(BIOS_SPEW, "Run returns %d\n", index);
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auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0;
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0);
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index = run(index);
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printk(BIOS_SPEW, "Run returns %d\n", index);
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auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0;
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auxout[1] = 0x01000000;
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/* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
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index = run(index);
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auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8;
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auxout[1] = 0x0a840000;
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/*(DP_LINK_BW_2_7 &0xa)|0x0000840a*/
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auxout[2] = 0x00000000;
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auxout[3] = 0x01000000;
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0);
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index = run(index);
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auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
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auxout[1] = 0x21000000;
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/* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE |
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* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
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index = run(index);
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auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3;
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auxout[1] = 0x00000000;
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/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0);
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index = run(index);
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auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5;
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5);
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index = run(index);
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auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
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auxout[1] = 0x22000000;
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/* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE |
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* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
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index = run(index);
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auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3;
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auxout[1] = 0x00000000;
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/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0);
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index = run(index);
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auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5;
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5);
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index = run(index);
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auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
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auxout[1] = 0x00000000;
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/* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE |
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* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/
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intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
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index = run(index);
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if (index != niodefs)
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printk(BIOS_ERR, "Left over IO work in i915_lightup"
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" -- this is likely a table error. "
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"Only %d of %d were done.\n", index, niodefs);
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printk(BIOS_SPEW, "DONE startup\n");
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verbose = 0;
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/* GTT is the Global Translation Table for the graphics pipeline.
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* It is used to translate graphics addresses to physical
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* memory addresses. As in the CPU, GTTs map 4K pages.
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* There are 32 bits per pixel, or 4 bytes,
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* which means 1024 pixels per page.
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* There are 4250 GTTs on Link:
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* 2650 (X) * 1700 (Y) pixels / 1024 pixels per page.
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* The setgtt function adds a further bit of flexibility:
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* it allows you to set a range (the first two parameters) to point
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* to a physical address (third parameter);the physical address is
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* incremented by a count (fourth parameter) for each GTT in the
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* range.
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* Why do it this way? For ultrafast startup,
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* we can point all the GTT entries to point to one page,
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* and set that page to 0s:
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* memset(physbase, 0, 4096);
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* setgtt(0, 4250, physbase, 0);
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* this takes about 2 ms, and is a win because zeroing
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* the page takes a up to 200 ms. We will be exploiting this
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* trick in a later rev of this code.
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* This call sets the GTT to point to a linear range of pages
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* starting at physbase.
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*/
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setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
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printk(BIOS_SPEW, "memset %p to 0 for %d bytes\n",
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(void *)graphics, FRAME_BUFFER_BYTES);
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memset((void *)graphics, 0, FRAME_BUFFER_BYTES);
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printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds());
|
||||
set_vbe_mode_info_valid(&edid, (uintptr_t)graphics);
|
||||
i915_init_done = 1;
|
||||
return i915_init_done;
|
||||
}
|
||||
|
|
@ -1,355 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include "i915io.h"
|
||||
|
||||
struct iodef iodefs[] = {
|
||||
{V, 0},
|
||||
{W, 1, "", PCH_GMBUS0, 0x00000000, 0},
|
||||
{R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0},
|
||||
{R, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x0 << 16) | ( /* Tx */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x190 << 16) | ( /* T5 */ 0x7d0 << 0) | 0x019007d0, 0},
|
||||
{W, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x15e << 16) | ( /* Tx */ 0x7d0 << 0) | 0x015e07d0, 0},
|
||||
{M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables", 0x0, 0xcf8e64, 0},
|
||||
{R, 50, "", FORCEWAKE_MT_ACK, 0x00000001, 10},
|
||||
{W, 1, "", FORCEWAKE_MT, 0x00010001, 0},
|
||||
{R, 1, "", FORCEWAKE_MT, 0x00010001, 0},
|
||||
{R, 1, "", FORCEWAKE_MT_ACK, 0x00000001, 0},
|
||||
{R, 1, "", 0x13805c, 0x40000000, 0},
|
||||
{R, 1, "", 0xa180, 0x84100020, 0},
|
||||
{W, 1, "", FORCEWAKE_MT, 0x00010000, 0},
|
||||
{R, 1, "", 0x120000, 0x00000000, 0},
|
||||
{M, 1, "[drm:intel_init_display], Using MT version of forcewake", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:intel_modeset_init], 3 display pipes available.", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{R, 1, "", 0x72008, 0x00000000, 0},
|
||||
{W, 1, "", 0x72008, 0x00000000, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{R, 1, "", 0x72008, 0x00000000, 0},
|
||||
{W, 1, "", 0x72008, 0x00000000, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{R, 1, "", 0x72008, 0x00000000, 0},
|
||||
{W, 1, "", 0x72008, 0x00000000, 300},
|
||||
{W, 1, "", CPU_VGACNTRL, 0x80000000, 0},
|
||||
{R, 1, "", CPU_VGACNTRL, 0x80000000, 0},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
|
||||
{R, 1, "", PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_DPA | ( /* PANEL_POWER_UP_DELAY */ 0x7d0 << 16) | ( /* PANEL_LIGHT_ON_DELAY */ 0x7d0 << 0) | 0x47d007d0, 0},
|
||||
{R, 1, "", PCH_PP_OFF_DELAYS, ( /* PANEL_POWER_DOWN_DELAY */ 0x1f4 << 16) | ( /* PANEL_LIGHT_OFF_DELAY */ 0x7d0 << 0) | 0x01f407d0, 0},
|
||||
{R, 1, "", PCH_PP_DIVISOR, 0x00186906, 0},
|
||||
{M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500t11_t12 6000", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_init], panel power up delay 200,power down" "delay 50, power cycle delay 600", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000", 0x0, 0xcf8e64, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, 0x00000000, 0},
|
||||
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A", 0x0, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{I,},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0x00000000, 0},
|
||||
{R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, 0},
|
||||
{M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 " "has_pch_edp 0has_cpu_edp 1 has_ck505 0", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_DREF_CONTROL, 0x00000000, 0},
|
||||
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 0},
|
||||
{R, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 200},
|
||||
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0},
|
||||
{R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200},
|
||||
{W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0},
|
||||
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", 0x9404, 0x00002000, 0},
|
||||
{W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0},
|
||||
{W, 1, "", IVB_CHICKEN3, 0x00000024, 0},
|
||||
{W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0},
|
||||
{W, 1, "", 0xb01c, 0x3c4fff8c, 0},
|
||||
{W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0},
|
||||
{R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0},
|
||||
{W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0},
|
||||
{R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0},
|
||||
{W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0},
|
||||
{R, 1, "", _DSPAADDR, 0x00000000, 0},
|
||||
{W, 1, "", _DSPAADDR, 0x00000000, 0},
|
||||
{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
|
||||
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
|
||||
{R, 1, "", _DSPBCNTR, 0x00000000, 0},
|
||||
{W, 1, "", _DSPBCNTR, 0x00004000, 0},
|
||||
{R, 1, "", _DSPBADDR, 0x00000000, 0},
|
||||
{W, 1, "", _DSPBADDR, 0x00000000, 0},
|
||||
{R, 1, "", _DSPBSURF, 0x00000000, 0},
|
||||
{W, 1, "", _DSPBSURF, 0x00000000, 0},
|
||||
{R, 1, "", _DVSACNTR, 0x00000000, 0},
|
||||
{W, 1, "", _DVSACNTR, DVS_TRICKLE_FEED_DISABLE | 0x00004000, 0},
|
||||
{R, 1, "", _DVSALINOFF, 0x00000000, 0},
|
||||
{W, 1, "", _DVSALINOFF, 0x00000000, 0},
|
||||
{R, 1, "", _DVSASURF, 0x00000000, 0},
|
||||
{W, 1, "", _DVSASURF, 0x00000000, 0},
|
||||
{W, 1, "", SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 0x20000000, 0},
|
||||
{R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0},
|
||||
{W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0},
|
||||
{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0},
|
||||
{W, 1, "", _TRANSB_CHICKEN2, TRANS_CHICKEN2_TIMING_OVERRIDE | 0x80000000, 0},
|
||||
{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_setup_crtcs], ", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],[ENCODER:7:TMDS-7]", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{I,},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0},
|
||||
{R, 2, "", PCH_DP_D, 0x00000004, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0},
|
||||
{M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 1749 0x48 0xa", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", _TRANSA_DATA_M1, 0x00000000, 0},
|
||||
{W, 1, "", _TRANSA_DATA_N1, 0x00000000, 0},
|
||||
{W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, 0},
|
||||
{W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, 0},
|
||||
{W, 1, "", _PCH_FPA1, 0x00020e08, 0},
|
||||
{W, 1, "", _VSYNCSHIFT_A, 0x00000000, 0},
|
||||
{W, 1, "", _HTOTAL_A, 0x0a9f09ff, 0},
|
||||
{W, 1, "", _HBLANK_A, 0x0a9f09ff, 0},
|
||||
{W, 1, "", _HSYNC_A, 0x0a4f0a2f, 0},
|
||||
{W, 1, "", _VTOTAL_A, 0x06d406a3, 0},
|
||||
{W, 1, "", _VBLANK_A, 0x06d406a3, 0},
|
||||
{W, 1, "", _VSYNC_A, 0x06b006a6, 0},
|
||||
{W, 1, "", _PIPEASRC, 0x09ff06a3, 0},
|
||||
{W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, 0},
|
||||
{W, 1, "", _PIPEA_DATA_N1, 0x0083d600, 0},
|
||||
{W, 1, "", _PIPEA_LINK_M1, 0x00045a42, 0},
|
||||
{W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, 0},
|
||||
{M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
|
||||
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 500},
|
||||
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
|
||||
{R, 4562, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
|
||||
{R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
|
||||
{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
|
||||
{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", _DSPASTRIDE, 0x00002800, 0},
|
||||
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
|
||||
{W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0},
|
||||
{W, 1, "", _DSPAADDR, 0x00000000, 0},
|
||||
{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0},
|
||||
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
|
||||
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane " "288, fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) | ( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0},
|
||||
{M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]set [MODE:0:2560x1700]", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_edp_pll_on], ", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
|
||||
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 200},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{R, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
|
||||
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
|
||||
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, " "fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) |( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0},
|
||||
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
|
||||
{W, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
|
||||
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00000040, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
|
||||
{W, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
|
||||
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0},
|
||||
{W, 2, "", SOUTH_CHICKEN1, 0x00000000, 0},
|
||||
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0},
|
||||
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
|
||||
{W, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
|
||||
{W, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
|
||||
{P, 1, "Set Palette"},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
|
||||
{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x80000050, 0},
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
|
||||
{R, 4533, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0},
|
||||
{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
|
||||
{W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0},
|
||||
{R, 1, "", _DSPAADDR, 0x00000000, 0},
|
||||
{W, 1, "", _DSPAADDR, 0x00000000, 0},
|
||||
{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
|
||||
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
|
||||
{R, 4392, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b", 0x0, 0xcf8e64, 0},
|
||||
{R, 4, "", PCH_PP_STATUS, /*undocbit3 | undocbit1 | */ 0x0000000a, 0},
|
||||
{R, 16983, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit1 | */ 0x9000000a, 0},
|
||||
{R, 17839, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit0 | */ 0x90000009, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0},
|
||||
{R, 2, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
|
||||
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
|
||||
{M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PRE_EMPHASIS_9_5 & 0xc00000) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8cdc4104, 0},
|
||||
{M, 1, "[drm:intel_dp_link_down], ", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 100},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0},
|
||||
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0},
|
||||
{R, 2, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{M, 1, "[drm:intel_dp_start_link_train], clock recovery OK", 0x0, 0x00000000, 0},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{M, 1, "[drm:ironlake_edp_backlight_on], ", 0x0, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
|
||||
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0},
|
||||
{R, 1, "", _PIPEADSL, 0x00000633, 500},
|
||||
{R, 1, "", _PIPEADSL, 0x00000652, 0},
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
|
||||
{R, 5085, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0},
|
||||
{I,},
|
||||
};
|
||||
|
||||
int niodefs = ARRAY_SIZE(iodefs);
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <drivers/intel/gma/i915_reg.h>
|
||||
#include <drivers/intel/gma/drm_dp_helper.h>
|
||||
|
||||
/* things that are, strangely, not defined anywhere? */
|
||||
#define PCH_PP_UNLOCK 0xabcd0000
|
||||
#define WMx_LP_SR_EN (1 << 31)
|
||||
|
||||
/* Google Link-specific defines */
|
||||
/* how many 4096-byte pages do we need for the framebuffer?
|
||||
* There are 32 bits per pixel, or 4 bytes,
|
||||
* which means 1024 pixels per page.
|
||||
* HencetThere are 4250 GTTs on Link:
|
||||
* 2650 (X) * 1700 (Y) pixels / 1024 pixels per page.
|
||||
*/
|
||||
#define FRAME_BUFFER_PAGES ((2560*1700)/1024)
|
||||
#define FRAME_BUFFER_BYTES (FRAME_BUFFER_PAGES*4096)
|
||||
|
||||
/* One-letter commands for code not meant to be ready for humans.
|
||||
* The code was generated by a set of programs/scripts.
|
||||
* M print out a kernel message
|
||||
* R read a register. We do these mainly to ensure that if hardware wanted
|
||||
* the register read, it was read; also, in debug, we can see what was expected
|
||||
* and what was found. This has proven *very* useful to get this debugged.
|
||||
* The udelay, if non-zero, will make sure there is a
|
||||
* udelay() call with the value.
|
||||
* The count is from the kernel and tells us how many times this read was done.
|
||||
* Also useful for debugging and the state
|
||||
* machine uses the info to drive a poll.
|
||||
* W Write a register
|
||||
* V set verbosity. It's a bit mask.
|
||||
* 0 -> nothing
|
||||
* 1 -> print kernel messages
|
||||
* 2 -> print IO ops
|
||||
* 4 -> print the number of times we spin on a register in a poll
|
||||
* 8 -> restore whatever the previous verbosity level was
|
||||
* (only one deep stack)
|
||||
*
|
||||
* Again, this is not really meant for human consumption. There is not a poll
|
||||
* operator as such because, sometimes, there is a read/write/read where the
|
||||
* second read is a poll, and this chipset is so touchy I'm reluctant to move
|
||||
* things around and/or delete too many reads.
|
||||
*/
|
||||
#define M 1
|
||||
#define R 2
|
||||
#define W 4
|
||||
#define V 8
|
||||
#define I 16
|
||||
#define P 32
|
||||
|
||||
struct iodef {
|
||||
unsigned char op;
|
||||
unsigned int count;
|
||||
const char *msg;
|
||||
unsigned long addr;
|
||||
unsigned long data;
|
||||
unsigned long udelay;
|
||||
};
|
||||
|
||||
/* i915.c */
|
||||
unsigned long io_i915_READ32(unsigned long addr);
|
||||
void io_i915_WRITE32(unsigned long val, unsigned long addr);
|
||||
|
||||
/* intel_dp.c */
|
||||
u32 pack_aux(u32 *src, int src_bytes);
|
||||
void unpack_aux(u32 src, u32 *dst, int dst_bytes);
|
||||
int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
|
||||
u32 *recv, int recv_size);
|
||||
|
|
@ -1,166 +0,0 @@
|
|||
/*
|
||||
* Copyright 2013 Google Inc.
|
||||
* Copyright © 2008 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Keith Packard <keithp@keithp.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <stdint.h>
|
||||
#include <delay.h>
|
||||
#include "i915io.h"
|
||||
|
||||
u32
|
||||
pack_aux(u32 *src32, int src_bytes)
|
||||
{
|
||||
u8 *src = (u8 *)src32;
|
||||
int i;
|
||||
u32 v = 0;
|
||||
|
||||
if (src_bytes > 4)
|
||||
src_bytes = 4;
|
||||
for (i = 0; i < src_bytes; i++)
|
||||
v |= ((u32) src[i]) << ((3-i) * 8);
|
||||
return v;
|
||||
}
|
||||
|
||||
void
|
||||
unpack_aux(u32 src, u32 *dst32, int dst_bytes)
|
||||
{
|
||||
u8 *dst = (u8 *)dst32;
|
||||
|
||||
int i;
|
||||
if (dst_bytes > 4)
|
||||
dst_bytes = 4;
|
||||
for (i = 0; i < dst_bytes; i++)
|
||||
dst[i] = src >> ((3-i) * 8);
|
||||
}
|
||||
|
||||
int
|
||||
intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
|
||||
u32 *recv, int recv_size)
|
||||
{
|
||||
int i;
|
||||
int recv_bytes;
|
||||
u32 status;
|
||||
u32 aux_clock_divider;
|
||||
int try, precharge = 5;
|
||||
|
||||
/* The clock divider is based off the hrawclk,
|
||||
* and would like to run at 2MHz. So, take the
|
||||
* hrawclk value and divide by 2 and use that
|
||||
*
|
||||
* Note that PCH attached eDP panels should use a 125MHz input
|
||||
* clock divider.
|
||||
*/
|
||||
/* 200 on link */
|
||||
aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
|
||||
|
||||
/* Try to wait for any previous AUX channel activity */
|
||||
for (try = 0; try < 3; try++) {
|
||||
status = io_i915_READ32(ch_ctl);
|
||||
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
||||
break;
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
if (try == 3) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n",
|
||||
io_i915_READ32(ch_ctl));
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Must try at least 3 times according to DP spec */
|
||||
for (try = 0; try < 5; try++) {
|
||||
/* Load the send data into the aux channel data registers */
|
||||
for (i = 0; i < send_bytes; i += 4)
|
||||
io_i915_WRITE32(send[i], ch_data + i);
|
||||
|
||||
/* Send the command and wait for it to complete */
|
||||
io_i915_WRITE32(
|
||||
DP_AUX_CH_CTL_SEND_BUSY |
|
||||
DP_AUX_CH_CTL_TIME_OUT_400us |
|
||||
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
|
||||
(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
|
||||
(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
|
||||
DP_AUX_CH_CTL_DONE |
|
||||
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
|
||||
for (;;) {
|
||||
status = io_i915_READ32(ch_ctl);
|
||||
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
||||
break;
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
/* Clear done status and any errors */
|
||||
io_i915_WRITE32(
|
||||
status |
|
||||
DP_AUX_CH_CTL_DONE |
|
||||
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
|
||||
|
||||
if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR))
|
||||
continue;
|
||||
if (status & DP_AUX_CH_CTL_DONE)
|
||||
break;
|
||||
}
|
||||
|
||||
if ((status & DP_AUX_CH_CTL_DONE) == 0) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for timeout or receive error.
|
||||
* Timeouts occur when the sink is not connected
|
||||
*/
|
||||
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Timeouts occur when the device isn't connected, so they're
|
||||
* "normal" -- don't fill the kernel log with these */
|
||||
if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Unload any bytes sent back from the other side */
|
||||
recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
|
||||
DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
|
||||
if (recv_bytes > recv_size)
|
||||
recv_bytes = recv_size;
|
||||
|
||||
for (i = 0; i < recv_bytes; i += 4)
|
||||
unpack_aux(io_i915_READ32(ch_data + i),
|
||||
recv + i, recv_bytes - i);
|
||||
|
||||
return recv_bytes;
|
||||
}
|
||||
Loading…
Reference in New Issue