GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/poppy: Nami - invoke power cycle of FPMCU on startup 

Add functionality such that the FPMCU is power cycled long enough
on boot to ensure proper reset.

This solution relies solely on coreboot to sequence the power and reset
signals appropriately (150ms on boot).

BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami.
Confirmed power is off for 150ms seconds on boot.
Confirmed RCC_CSR of FPMCU indicates power cycle occurred.
Confirmed reset is de-asserted approx 3ms after power application
(target >2.5ms)

Change-Id: I21eb85dc11e0ea0eb5de8a6092b01663d3c3df91
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68820
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Tarun Tuli 2022-10-25 18:57:34 +00:00 committed by Eric Lai
parent 4843ded47c
commit 2e6fa8206e
2 changed files with 75 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
src/mainboard/google/poppy/variants/nami/gpio.c
View File

@ -404,7 +404,7 @@ static const struct pad_config fpmcu_gpio_table[] = {
/* B1 : CORE_VID1 ==> FPMCU_INT_L */ /* B1 : CORE_VID1 ==> FPMCU_INT_L */
PAD_CFG_GPI_SCI(GPP_B1, UP_20K, DEEP, EDGE_SINGLE, INVERT), PAD_CFG_GPI_SCI(GPP_B1, UP_20K, DEEP, EDGE_SINGLE, INVERT),
/* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */ /* B11 : EXT_PWR_GATE# ==> PCH_FP_PWR_EN */
PAD_CFG_GPO(GPP_B11, 1, DEEP), PAD_CFG_GPO(GPP_B11, 0, DEEP),
/* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */ /* B19 : GSPI1_CS# ==> PCH_SPI_FP_CS# */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */ /* B20 : GSPI1_CLK ==> PCH_SPI_FP_CLK */
@ -416,13 +416,48 @@ static const struct pad_config fpmcu_gpio_table[] = {
/* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */
PAD_CFG_GPO(GPP_C3, 0, DEEP), PAD_CFG_GPO(GPP_C3, 0, DEEP),
/* C9 : UART0_TXD ==> FP_RST_ODL */ /* C9 : UART0_TXD ==> FP_RST_ODL */
PAD_CFG_GPO(GPP_C9, 1, DEEP), PAD_CFG_GPO(GPP_C9, 0, DEEP),
/* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */
PAD_CFG_GPO(GPP_D5, 0, DEEP), PAD_CFG_GPO(GPP_D5, 0, DEEP),
/* D17 : DMIC_CLK1 ==> NC */ /* D17 : DMIC_CLK1 ==> NC */
PAD_NC(GPP_D17, NONE), PAD_NC(GPP_D17, NONE),
}; };
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
uint32_t sku_id = variant_board_sku();
const struct pad_config *board_gpio_tables;
switch (sku_id) {
case SKU_0_EKKO:
case SKU_1_EKKO:
case SKU_2_EKKO:
case SKU_3_EKKO:
case SKU_4_EKKO:
case SKU_5_EKKO:
case SKU_6_EKKO:
case SKU_7_EKKO:
case SKU_0_BARD:
case SKU_1_BARD:
case SKU_2_BARD:
case SKU_3_BARD:
case SKU_4_BARD:
case SKU_5_BARD:
case SKU_6_BARD:
case SKU_7_BARD:
*num = ARRAY_SIZE(fpmcu_gpio_table);
board_gpio_tables = fpmcu_gpio_table;
break;
default:
/* Initialized in variant_sku_gpio_table */
*num = 0;
board_gpio_tables = NULL;
break;
}
return board_gpio_tables;
}
const struct pad_config *variant_sku_gpio_table(size_t *num) const struct pad_config *variant_sku_gpio_table(size_t *num)
{ {
uint32_t sku_id = variant_board_sku(); uint32_t sku_id = variant_board_sku();
@ -468,8 +503,9 @@ const struct pad_config *variant_sku_gpio_table(size_t *num)
case SKU_5_BARD: case SKU_5_BARD:
case SKU_6_BARD: case SKU_6_BARD:
case SKU_7_BARD: case SKU_7_BARD:
*num = ARRAY_SIZE(fpmcu_gpio_table); /* Initialized in variant_romstage_gpio_table */
board_gpio_tables = fpmcu_gpio_table; *num = 0;
board_gpio_tables = NULL;
break; break;
default: default:
*num = ARRAY_SIZE(nami_default_sku_gpio_table); *num = ARRAY_SIZE(nami_default_sku_gpio_table);

35
src/mainboard/google/poppy/variants/nami/mainboard.c
View File

@ -15,6 +15,8 @@
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include <string.h> #include <string.h>
#include <variant/sku.h> #include <variant/sku.h>
#include <gpio.h>
#include <delay.h>
#define PL2_I7_SKU 44 #define PL2_I7_SKU 44
#define PL2_DEFAULT 29 #define PL2_DEFAULT 29
@ -299,3 +301,36 @@ void variant_devtree_update(void)
sku_overwrite_mapping[oem_index].dc_loadline[i]; sku_overwrite_mapping[oem_index].dc_loadline[i];
} }
} }
void variant_final(void)
{
uint32_t sku_id = variant_board_sku();
switch (sku_id) {
case SKU_0_BARD:
case SKU_1_BARD:
case SKU_2_BARD:
case SKU_3_BARD:
case SKU_4_BARD:
case SKU_5_BARD:
case SKU_6_BARD:
case SKU_7_BARD:
case SKU_0_EKKO:
case SKU_1_EKKO:
case SKU_2_EKKO:
case SKU_3_EKKO:
case SKU_4_EKKO:
case SKU_5_EKKO:
case SKU_6_EKKO:
case SKU_7_EKKO:
/* Enable FPMCU late in the boot process to achieve
* ~150ms of power off time in total.
*/
gpio_output(GPP_B11, 1); /* PCH_FP_PWR_EN */
mdelay(3);
gpio_output(GPP_C9, 1); /* FP_RST_ODL */
break;
default:
break;
}
}