fsp/gop: Add running the GOP to the choice of gfx init

The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:

  * Drop confusing config GOP_SUPPORT,
  * Add HAVE_FSP_GOP to chipsets that support it,
  * Make running the GOP an option for FSP2.0 by returning 0
    in random VBT getters.

Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Nico Huber 2017-05-22 15:58:03 +02:00 committed by Nico Huber
parent d4ebeaf475
commit 2e7f6ccafc
17 changed files with 46 additions and 38 deletions

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@ -72,7 +72,6 @@
<li>Set the CPU_MICROCODE_CBFS_LOC</li>
<li>Set the FSP_IMAGE_ID_STRING</li>
<li>Set the FSP_LOC</li>
<li>Disable GOP_SUPPORT</li>
<li>No payload</li>
<li>Choose the default value for all other options</li>
</ol>

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@ -33,6 +33,12 @@ config HAVE_LINEAR_FRAMEBUFFER
Selected by graphics drivers that can set up a generic linear
framebuffer.
config HAVE_FSP_GOP
bool
help
Selected by drivers that support to run a blob that implements
the Graphics Output Protocol (GOP).
config MAINBOARD_HAS_NATIVE_VGA_INIT
def_bool n
help
@ -76,6 +82,15 @@ config MAINBOARD_USE_LIBGFXINIT
Use the SPARK library `libgfxinit` for the native graphics
initialization. This requires an Ada toolchain.
config RUN_FSP_GOP
bool "Run a GOP driver"
depends on HAVE_FSP_GOP
select HAVE_LINEAR_FRAMEBUFFER
help
Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support
to run a GOP blob. This option enables graphics initialization with
such a blob.
# TODO: Explain differences (if any) for onboard cards.
config VGA_ROM_RUN
bool "Run VGA Option ROMs"

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@ -16,6 +16,7 @@
config PLATFORM_USES_FSP1_1
bool
select UEFI_2_4_BINDING
select ADD_VBT_DATA_FILE if RUN_FSP_GOP
help
Does the code require the Intel Firmware Support Package?
@ -88,12 +89,6 @@ config FSP_USES_UPD
If this FSP uses UPD/VPD data regions, select this in the chipset
Kconfig.
config GOP_SUPPORT
bool "Enable GOP support"
default n
select ADD_VBT_DATA_FILE
select HAVE_LINEAR_FRAMEBUFFER
config USE_GENERIC_FSP_CAR_INC
bool
default n

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@ -32,13 +32,13 @@ romstage-y += stack.c
romstage-y += stage_cache.c
romstage-$(CONFIG_MMA) += mma_core.c
ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c
ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c
ramstage-y += fsp_relocate.c
ramstage-y += fsp_util.c
ramstage-y += hob.c
ramstage-y += ramstage.c
ramstage-y += stage_cache.c
ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
ramstage-$(CONFIG_RUN_FSP_GOP) += vbt.c
ramstage-$(CONFIG_MMA) += mma_core.c
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include

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@ -119,7 +119,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
soc_silicon_init_params(&silicon_init_params);
/* Locate VBT and pass to FSP GOP */
if (IS_ENABLED(CONFIG_GOP_SUPPORT))
if (IS_ENABLED(CONFIG_RUN_FSP_GOP))
load_vbt(is_s3_wakeup, &silicon_init_params);
mainboard_silicon_init_params(&silicon_init_params);
@ -141,7 +141,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
/* Mark graphics init done after SiliconInit if VBT was provided */
#if IS_ENABLED(CONFIG_GOP_SUPPORT)
#if IS_ENABLED(CONFIG_RUN_FSP_GOP)
/* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs
* to be #if'd out instead of using if (). */
if (silicon_init_params.GraphicsConfigPtr)

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@ -16,7 +16,6 @@
config PLATFORM_USES_FSP2_0
bool
select UDK_2015_BINDING
select HAVE_LINEAR_FRAMEBUFFER
help
Include FSP 2.0 wrappers and functionality

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@ -27,7 +27,7 @@ romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
romstage-$(CONFIG_MMA) += mma_core.c
ramstage-y += debug.c
ramstage-y += graphics.c
ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c
ramstage-y += hand_off_block.c
ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c

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@ -85,7 +85,11 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr,
const struct region_device *rdev);
/* Load a vbt.bin file for graphics. Returns 0 if a valid VBT is not found. */
#if IS_ENABLED(CONFIG_RUN_FSP_GOP)
uintptr_t fsp_load_vbt(void);
#else
static inline uintptr_t fsp_load_vbt(void) { return 0; }
#endif
/* Get igd framebuffer bar from SoC */
uintptr_t fsp_soc_get_igd_bar(void);

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@ -42,9 +42,9 @@ config MAINBOARD_VENDOR
string
default "Google"
if !GOP_SUPPORT
config VGA_BIOS_FILE
string
depends on VGA_BIOS
default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin"
help
The C0 version of the video bios gets computed from this name
@ -53,13 +53,12 @@ config VGA_BIOS_FILE
config VGA_BIOS_ID
string
depends on VGA_BIOS
default "8086,22b0"
help
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
in soc/intel/braswell/Makefile.inc as 8086,22b1
endif #GOP_SUPPORT
config GBB_HWID
string
depends on CHROMEOS

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@ -35,9 +35,9 @@ config MAINBOARD_VENDOR
string
default "Intel"
if !GOP_SUPPORT
config VGA_BIOS_FILE
string
depends on VGA_BIOS
default "3rdparty/blobs/mainboard/intel/strago/vgabios.bin"
help
The C0 version of the video bios gets computed from this name
@ -46,13 +46,12 @@ config VGA_BIOS_FILE
config VGA_BIOS_ID
string
depends on VGA_BIOS
default "8086,22b0"
help
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
in soc/intel/braswell/Makefile.inc as 8086,22b1
endif #GOP_SUPPORT
config EC_GOOGLE_CHROMEEC_BOARDNAME
string
default "strago"

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@ -78,7 +78,8 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_GFX_OPREGION
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CSE
select ADD_VBT_DATA_FILE
select ADD_VBT_DATA_FILE if RUN_FSP_GOP
select HAVE_FSP_GOP
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC

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@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS
select USE_GENERIC_FSP_CAR_INC
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
select HAVE_FSP_GOP
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE

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@ -20,7 +20,7 @@ ramstage-y += cpu.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += emmc.c
ramstage-y += gpio.c
ifeq ($(CONFIG_GOP_SUPPORT),n)
ifneq ($(CONFIG_RUN_FSP_GOP),y)
ramstage-y += gfx.c
endif
ramstage-y += gpio_support.c
@ -59,7 +59,6 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/braswell
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
ifneq ($(CONFIG_GOP_SUPPORT),y)
ifneq ($(CONFIG_VGA_BIOS_FILE),)
#we will assume that the vbios names will remain as they are now: vgabios.bin and vgabios_c0.bin
BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)))
@ -67,8 +66,6 @@ BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FI
cbfs-files-$(CONFIG_VGA_BIOS) += pci8086,22b1.rom
pci8086,22b1.rom-file := $(BRASWELL_C0_VBIOS)
pci8086,22b1.rom-type := optionrom
endif # ifneq ($(CONFIG_GOP_SUPPORT),y)
endif # ifneq ($(CONFIG_VGA_BIOS_FILE),)
endif # ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)

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@ -482,7 +482,7 @@ unsigned long southcluster_write_acpi_tables(device_t device,
current = acpi_write_hpet(device, current, rsdp);
current = acpi_align_current(current);
#if CONFIG_GOP_SUPPORT
if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) {
igd_opregion_t *opregion;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
@ -490,7 +490,7 @@ unsigned long southcluster_write_acpi_tables(device_t device,
init_igd_opregion(opregion);
current += sizeof(igd_opregion_t);
current = acpi_align_current(current);
#endif
}
ssdt2 = (acpi_header_t *)current;
memset(ssdt2, 0, sizeof(acpi_header_t));
@ -544,7 +544,6 @@ __attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
{
}
#if CONFIG_GOP_SUPPORT
/* Reading VBT table from flash */
static void get_fsp_vbt(igd_opregion_t *opregion)
{
@ -615,4 +614,3 @@ int init_igd_opregion(igd_opregion_t *opregion)
return 0;
}
#endif

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@ -20,10 +20,8 @@
#include <arch/acpi.h>
#include <soc/nvs.h>
#if CONFIG_GOP_SUPPORT
#include <fsp/gma.h>
int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void acpi_fill_in_fadt(acpi_fadt_t *fadt);

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@ -47,6 +47,9 @@ void *vbt_get(struct region_device *rdev)
{
void *vbt_data;
if (!IS_ENABLED(CONFIG_RUN_FSP_GOP))
return NULL;
/* Normal mode and S3 resume path PEIM GFX init is not needed.
* Passing NULL as VBT will not make PEIM GFX to execute. */
if (acpi_is_wakeup_s3())

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@ -77,6 +77,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE
select UDELAY_TSC
select ACPI_NHLT
select HAVE_FSP_GOP
config MAINBOARD_USES_FSP2_0
bool
@ -87,7 +88,7 @@ config USE_FSP2_0_DRIVER
depends on MAINBOARD_USES_FSP2_0
default y if MAINBOARD_USES_FSP2_0
select PLATFORM_USES_FSP2_0
select ADD_VBT_DATA_FILE
select ADD_VBT_DATA_FILE if RUN_FSP_GOP
select SOC_INTEL_COMMON_GFX_OPREGION
select POSTCAR_CONSOLE
select POSTCAR_STAGE
@ -97,7 +98,6 @@ config USE_FSP1_1_DRIVER
depends on !MAINBOARD_USES_FSP2_0
default y if !MAINBOARD_USES_FSP2_0
select PLATFORM_USES_FSP1_1
select GOP_SUPPORT
select DISPLAY_FSP_ENTRY_POINTS
config CHROMEOS