From 2e8e0601fda4a5a1b2a3b1f18fd1c20608e423df Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 13 Aug 2022 19:50:28 +0200 Subject: [PATCH] soc/intel/common/block/cse: Tidy up table in comment Adjust an ASCII art table so that it looks good: consistent padding and aligned table borders. Change-Id: I26196f969406e03f320256b0c3a337282f636914 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/66707 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/common/block/cse/cse_lite.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 2e8a868dc8..40ae9953ec 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -34,9 +34,9 @@ * CSE Firmware supports 3 boot partitions. For CSE Lite SKU, only 2 boot partitions are * used and 3rd boot partition is set to BP_STATUS_PARTITION_NOT_PRESENT. * CSE Lite SKU Image Layout: - * ------------- ------------------ -------------------- - * |CSE REGION | => | RO | DATA | RW | => | BP1 | DATA | BP2 | - * ------------- ------------------ -------------------- + * +------------+ +----+------+----+ +-----+------+-----+ + * | CSE REGION | => | RO | DATA | RW | => | BP1 | DATA | BP2 | + * +------------+ +----+------+----+ +-----+------+-----+ */ #define CSE_MAX_BOOT_PARTITIONS 3