mb/google/rex/var/rex0: Configure I2C timing for I2C devices
Configure I2C0/1/3/4 timing in devicetree to ensure I2C devices meet timing requirement. Note that I2C5 timing will be updated separately when the tuning done BUG=b:280559903 TEST=Build and check I2C devices timing meet spec. | | I2C0-Codec | I2C0-WFC | I2C1 | I2C3 | I2C4 | |-------------|------------|----------|--------|-------|---------| | FSMB(KHz) | 347 | 343.2 | 389.3 | 393.7 | 381.9 | | TLOW(us) | 2.1 | 2.093 | 1.895 | 1.902 | 1.953 | | THIGH(us) | 0.647 | 0.628 | 0.602 | 0.62 | 0.612 | | THD:STA(us) | 0.633 | 0.64 | 0.601 | 0.6 | 0.601 | | TSU:STA(us) | 0.617 | 0.621 | 0.619 | 0.659 | 0.61 | | TSU:STO(us) | 0.656 | 0.647 | 0.667 | 0.727 | 0.634 | | TBUF(us) | 86.15 | >14.088 | >9.833 | >8 | >10.366 | Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I5421e4fe68e856bbe9f19544954a94670c895a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75150 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
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@ -116,26 +116,26 @@ chip soc/intel/meteorlake
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.fall_time_ns = 400,
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.rise_time_ns = 400,
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.fall_time_ns = 350,
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.data_hold_time_ns = 50,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.rise_time_ns = 600,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 650,
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.rise_time_ns = 600,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[4] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 600,
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.rise_time_ns = 550,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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