GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Force SB800 bootblock to use I/O for PCI config 

If PCI config cycles use MMIO instead of I/O in the bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O.

Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/630
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Dave Frodin 2012-02-02 14:56:23 -07:00 committed by Marc Jones
parent d8d8c63cf7
commit 2eacc0eec2
1 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/southbridge/amd/sb800/bootblock.c
View File

@ -39,15 +39,15 @@ static void sb800_enable_rom(void)
dev = PCI_DEV(0, 0x14, 3);
/* Decode variable LPC ROM address ranges 1 and 2. */
reg8 = pci_read_config8(dev, 0x48);
reg8 = pci_io_read_config8(dev, 0x48);
reg8 |= (1 << 3) | (1 << 4);
pci_write_config8(dev, 0x48, reg8);
pci_io_write_config8(dev, 0x48, reg8);
/* LPC ROM address range 1: */
/* Enable LPC ROM range mirroring start at 0x000e(0000). */
pci_write_config16(dev, 0x68, 0x000e);
pci_io_write_config16(dev, 0x68, 0x000e);
/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
pci_write_config16(dev, 0x6a, 0x000f);
pci_io_write_config16(dev, 0x6a, 0x000f);
/* LPC ROM address range 2: */
/*
@ -57,9 +57,9 @@ static void sb800_enable_rom(void)
* 0xffe0(0000): 2MB
* 0xffc0(0000): 4MB
*/
pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
/* Enable LPC ROM range end at 0xffff(ffff). */
pci_write_config16(dev, 0x6e, 0xffff);
pci_io_write_config16(dev, 0x6e, 0xffff);
}
static void bootblock_southbridge_init(void)