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soc/intel/common: Fix 16-bit read/write PCI_COMMAND register 

Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2020-04-29 09:57:05 +02:00 committed by Patrick Georgi
parent b887adf7a5
commit 2ec1c13ac4
8 changed files with 19 additions and 24 deletions
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10
src/soc/intel/common/block/cse/cse.c
View File

@ -75,7 +75,7 @@ void heci_init(uintptr_t tempbar)
#else
struct device *dev = PCH_DEV_CSE;
#endif
u8 pcireg;
u16 pcireg;
/* Assume it is already initialized, nothing else to do */
if (cse.sec_bar)
@ -87,18 +87,16 @@ void heci_init(uintptr_t tempbar)
/* Assign Resources to HECI1 */
/* Clear BIT 1-2 of Command Register */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg = pci_read_config16(dev, PCI_COMMAND);
pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
pci_write_config8(dev, PCI_COMMAND, pcireg);
pci_write_config16(dev, PCI_COMMAND, pcireg);
/* Program Temporary BAR for HECI1 */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
/* Enable Bus Master and MMIO Space */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config8(dev, PCI_COMMAND, pcireg);
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
cse.sec_bar = tempbar;
}

10
src/soc/intel/common/block/fast_spi/fast_spi.c
View File

@ -260,22 +260,20 @@ void fast_spi_early_init(uintptr_t spi_base_address)
#else
struct device *dev = PCH_DEV_SPI;
#endif
uint8_t pcireg;
uint16_t pcireg;
/* Assign Resources to SPI Controller */
/* Clear BIT 1-2 SPI Command Register */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg = pci_read_config16(dev, PCI_COMMAND);
pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
pci_write_config8(dev, PCI_COMMAND, pcireg);
pci_write_config16(dev, PCI_COMMAND, pcireg);
/* Program Temporary BAR for SPI */
pci_write_config32(dev, PCI_BASE_ADDRESS_0,
spi_base_address | PCI_BASE_ADDRESS_SPACE_MEMORY);
/* Enable Bus Master and MMIO Space */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config8(dev, PCI_COMMAND, pcireg);
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Initialize SPI to allow BIOS to write/erase on flash. */
fast_spi_init();

2
src/soc/intel/common/block/i2c/i2c.c
View File

@ -69,7 +69,7 @@ static int lpss_i2c_early_init_bus(unsigned int bus)
/* Prepare early base address for access before memory */
base = dw_i2c_get_soc_early_base(bus);
pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
pci_write_config32(dev, PCI_COMMAND,
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Take device out of reset */

2
src/soc/intel/common/block/p2sb/p2sb.c
View File

@ -23,7 +23,7 @@ void p2sb_enable_bar(void)
pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0);
/* Enable P2SB MSE */
pci_write_config8(PCH_DEV_P2SB, PCI_COMMAND,
pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}

3
src/soc/intel/common/block/sata/sata.c
View File

@ -34,8 +34,7 @@ static void sata_final(struct device *dev)
u8 port_impl, temp;
/* Set Bus Master */
temp = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Read Ports Implemented (GHC_PI) */
port_impl = read8(ahcibar + SATA_ABAR_PORT_IMPLEMENTED);

4
src/soc/intel/common/block/scs/early_mmc.c
View File

@ -32,14 +32,14 @@ static void enable_mmc_controller_bar(void)
{
pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0,
PRERAM_MMC_BASE_ADDRESS);
pci_write_config32(PCH_DEV_EMMC, PCI_COMMAND,
pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
}
static void disable_mmc_controller_bar(void)
{
pci_write_config32(PCH_DEV_EMMC, PCI_BASE_ADDRESS_0, 0);
pci_write_config32(PCH_DEV_EMMC, PCI_COMMAND,
pci_write_config16(PCH_DEV_EMMC, PCI_COMMAND,
~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
}

8
src/soc/intel/common/block/smm/smihandler.c
View File

@ -139,7 +139,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) {
u32 reg32;
u16 reg16;
pci_devfn_t dev = PCI_DEV(bus, slot, func);
@ -152,9 +152,9 @@ static void busmaster_disable_on_bus(int bus)
continue;
/* Disable Bus Mastering for this one device */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, reg16);
/* If it's not a bridge, move on. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);

4
src/soc/intel/common/block/uart/uart.c
View File

@ -68,7 +68,7 @@ void uart_common_init(const struct device *device, uintptr_t baseaddr)
pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);
/* Enable memory access and bus master */
pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE);
pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE);
uart_lpss_init(device, baseaddr);
}
@ -109,7 +109,7 @@ bool uart_is_controller_initialized(void)
if (!base)
return false;
if ((pci_read_config32(dev, PCI_COMMAND) & UART_PCI_ENABLE)
if ((pci_read_config16(dev, PCI_COMMAND) & UART_PCI_ENABLE)
!= UART_PCI_ENABLE)
return false;