GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all 

the possible IRQs generated by the SIO. This included IRQ 7 as the default
parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's
own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards
that were setting it to prevent the conflict and crash when the MFGPT driver
loads.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones 2008-05-16 18:08:54 +00:00
parent 0fd8ccd7e7
commit 2ee5c9e21b
4 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/amd/db800/Config.lb
View File

@ -127,8 +127,8 @@ chip northbridge/amd/lx
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power.... # SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x000010da" register "lpc_serirq_enable" = "0x0000105a"
register "lpc_serirq_polarity" = "0x0000EF25" register "lpc_serirq_polarity" = "0x0000EFA5"
register "lpc_serirq_mode" = "1" register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700" register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash

4
src/mainboard/digitallogic/msm800sev/Config.lb
View File

@ -128,9 +128,9 @@ chip northbridge/amd/lx
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
# How to get these? Boot linux and do this: # How to get these? Boot linux and do this:
# rdmsr 0x51400025 # rdmsr 0x51400025
register "lpc_serirq_enable" = "0x000010da" register "lpc_serirq_enable" = "0x0000105a"
# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
register "lpc_serirq_polarity" = "0x0000EF25" register "lpc_serirq_polarity" = "0x0000EFA5"
# mode is high 10 bits (determined from code) # mode is high 10 bits (determined from code)
register "lpc_serirq_mode" = "1" register "lpc_serirq_mode" = "1"
# Don't yet know how to find this. # Don't yet know how to find this.

4
src/mainboard/iei/pcisa-lx-800-r10/Config.lb
View File

@ -78,8 +78,8 @@ chip northbridge/amd/lx
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
# SIRQ Mode = Active(Quiet) mode. Save power.... # SIRQ Mode = Active(Quiet) mode. Save power....
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
register "lpc_serirq_enable" = "0x000010da" register "lpc_serirq_enable" = "0x0000105a"
register "lpc_serirq_polarity" = "0x0000EF25" register "lpc_serirq_polarity" = "0x0000EFA5"
register "lpc_serirq_mode" = "1" register "lpc_serirq_mode" = "1"
register "enable_gpio_int_route" = "0x0D0C0700" register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash

4
src/mainboard/pcengines/alix1c/Config.lb
View File

@ -148,9 +148,9 @@ chip northbridge/amd/lx
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
# How to get these? Boot linux and do this: # How to get these? Boot linux and do this:
# rdmsr 0x51400025 # rdmsr 0x51400025
register "lpc_serirq_enable" = "0x000010da" register "lpc_serirq_enable" = "0x0000105a"
# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
register "lpc_serirq_polarity" = "0x0000EF25" register "lpc_serirq_polarity" = "0x0000EFA5"
# mode is high 10 bits (determined from code) # mode is high 10 bits (determined from code)
register "lpc_serirq_mode" = "1" register "lpc_serirq_mode" = "1"
# Don't yet know how to find this. # Don't yet know how to find this.