soc/intel/icelake: Pass FSP-M/S UPD as per ICL requirement
1. Gfx stolen memory requirement for ICL GFX 2. Enable PeiGraphicsPeim support Change-Id: I22dd14249b7402873f1ac07bee164ee7bee36414 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31955 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra
Subrata Banik
parent
a427ff0f50
commit
2ee8fe0094
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@ -254,10 +254,6 @@ struct soc_intel_icelake_config {
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/* Enable Pch iSCLK */
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uint8_t pch_isclk;
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/* Intel VT configuration */
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uint8_t VtdDisable;
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uint8_t VmxEnable;
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/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
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enum {
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PLATFORM_POR,
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@ -13,14 +13,203 @@
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <intelblocks/xdci.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <string.h>
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#include <intelblocks/mp_init.h>
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#include <fsp/ppi/mp_service_ppi.h>
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static void parse_devicetree(FSP_S_CONFIG *params)
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{
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struct device *dev = pcidev_on_root(0, 0);
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if (!dev) {
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printk(BIOS_ERR, "Could not find root device\n");
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return;
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}
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const struct soc_intel_icelake_config *config = dev->chip_info;
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for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
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params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
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for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
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params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
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params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
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params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
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}
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for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
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params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
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}
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/* UPD parameters to be initialized before SiliconInit */
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void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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{
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/* ToDo: update with UPD override as FSP matures */
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int i;
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FSP_S_CONFIG *params = &supd->FspsConfig;
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struct device *dev = SA_DEV_ROOT;
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config_t *config = dev->chip_info;
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/* Parse device tree and enable/disable devices */
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parse_devicetree(params);
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/* Load VBT before devicetree-specific config. */
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params->GraphicsConfigPtr = (uintptr_t)vbt_get();
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/* Set USB OC pin to 0 first */
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for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++)
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params->Usb2OverCurrentPin[i] = 0;
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for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++)
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params->Usb3OverCurrentPin[i] = 0;
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if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
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params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
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params->SkipMpInit = 0;
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} else {
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params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
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}
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mainboard_silicon_init_params(params);
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params->PeiGraphicsPeimInit = 1;
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params->GtFreqMax = 2;
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params->CdClock = 3;
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/* Unlock upper 8 bytes of RTC RAM */
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params->PchLockDownRtcMemoryLock = 0;
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params->CnviBtAudioOffload = config->CnviBtAudioOffload;
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/* SATA */
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dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
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if (!dev)
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params->SataEnable = 0;
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else {
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params->SataEnable = dev->enabled;
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params->SataMode = config->SataMode;
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params->SataSalpSupport = config->SataSalpSupport;
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memcpy(params->SataPortsEnable, config->SataPortsEnable,
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sizeof(params->SataPortsEnable));
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memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
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sizeof(params->SataPortsDevSlp));
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}
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/* Lan */
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dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 6);
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if (!dev)
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params->PchLanEnable = 0;
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else
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params->PchLanEnable = dev->enabled;
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/* Audio */
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params->PchHdaDspEnable = config->PchHdaDspEnable;
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params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda;
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params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0;
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params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1;
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params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0;
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params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1;
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params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2;
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params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1;
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params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2;
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params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3;
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params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4;
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/* disable Legacy PME */
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memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
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/* S0ix */
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params->PchPmSlpS0Enable = config->s0ix_enable;
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/* USB */
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for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
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params->PortUsb20Enable[i] =
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config->usb2_ports[i].enable;
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params->Usb2OverCurrentPin[i] =
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config->usb2_ports[i].ocpin;
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params->Usb2PhyPetxiset[i] =
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config->usb2_ports[i].pre_emp_bias;
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params->Usb2PhyTxiset[i] =
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config->usb2_ports[i].tx_bias;
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params->Usb2PhyPredeemp[i] =
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config->usb2_ports[i].tx_emp_enable;
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params->Usb2PhyPehalfbit[i] =
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config->usb2_ports[i].pre_emp_bit;
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}
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for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
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params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
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params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
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if (config->usb3_ports[i].tx_de_emp) {
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params->Usb3HsioTxDeEmphEnable[i] = 1;
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params->Usb3HsioTxDeEmph[i] =
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config->usb3_ports[i].tx_de_emp;
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}
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if (config->usb3_ports[i].tx_downscale_amp) {
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params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
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params->Usb3HsioTxDownscaleAmp[i] =
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config->usb3_ports[i].tx_downscale_amp;
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}
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}
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/* Enable xDCI controller if enabled in devicetree and allowed */
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dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
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if (!xdci_can_enable())
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dev->enabled = 0;
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params->XdciEnable = dev->enabled;
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/* PCI Express */
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for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
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if (config->PcieClkSrcUsage[i] == 0)
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config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
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}
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memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage,
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sizeof(config->PcieClkSrcUsage));
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memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
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sizeof(config->PcieClkSrcClkReq));
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/* eMMC */
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dev = pcidev_on_root(PCH_DEV_SLOT_STORAGE, 0);
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if (!dev)
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params->ScsEmmcEnabled = 0;
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else {
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params->ScsEmmcEnabled = dev->enabled;
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params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
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params->EmmcUseCustomDlls = config->EmmcUseCustomDlls;
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if (config->EmmcUseCustomDlls == 1) {
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params->EmmcTxCmdDelayRegValue =
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config->EmmcTxCmdDelayRegValue;
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params->EmmcTxDataDelay1RegValue =
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config->EmmcTxDataDelay1RegValue;
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params->EmmcTxDataDelay2RegValue =
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config->EmmcTxDataDelay2RegValue;
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params->EmmcRxCmdDataDelay1RegValue =
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config->EmmcRxCmdDataDelay1RegValue;
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params->EmmcRxCmdDataDelay2RegValue =
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config->EmmcRxCmdDataDelay2RegValue;
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params->EmmcRxStrobeDelayRegValue =
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config->EmmcRxStrobeDelayRegValue;
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}
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}
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/* SD */
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dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 5);
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if (!dev)
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params->ScsSdCardEnabled = 0;
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else {
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params->ScsSdCardEnabled = dev->enabled;
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params->SdCardPowerEnableActiveHigh =
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config->SdCardPowerEnableActiveHigh;
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}
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params->Heci3Enabled = config->Heci3Enabled;
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params->Device4Enable = config->Device4Enable;
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}
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/* Mainboard GPIO Configuration */
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@ -13,13 +13,72 @@
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <chip.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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const struct soc_intel_icelake_config *config)
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{
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unsigned int i;
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const struct device *dev = pcidev_on_root(0, 0);
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uint32_t mask = 0;
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/* Set IGD stolen size to 60MB. */
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m_cfg->IgdDvmt50PreAlloc = 0xFE;
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m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
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m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
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m_cfg->SaGv = config->SaGv;
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m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
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m_cfg->RMT = config->RMT;
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m_cfg->SkipMbpHob = 1;
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/* If Audio Codec is enabled, enable FSP UPD */
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if (!dev)
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m_cfg->PchHdaEnable = 0;
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else
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m_cfg->PchHdaEnable = dev->enabled;
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for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
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if (config->PcieRpEnable[i])
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mask |= (1 << i);
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}
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m_cfg->PcieRpEnableMask = mask;
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m_cfg->PrmrrSize = config->PrmrrSize;
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m_cfg->EnableC6Dram = config->enable_c6dram;
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/* Disable BIOS Guard */
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m_cfg->BiosGuard = 0;
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/* Disable Cpu Ratio Override temporary. */
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m_cfg->CpuRatio = 0;
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m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
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m_cfg->PcdDebugInterfaceFlags =
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CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10;
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/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
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m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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/* ToDo: update with UPD override as FSP matures */
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const struct device *dev = pcidev_on_root(0, 0);
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assert(dev != NULL);
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const struct soc_intel_icelake_config *config = dev->chip_info;
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FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
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soc_memory_init_params(m_cfg, config);
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/* Enable SMBus controller based on config */
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m_cfg->SmbusEnable = config->SmbusEnable;
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/* Set debug probe type */
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m_cfg->PlatformDebugConsent = config->DebugConsent;
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/* Vt-D config */
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m_cfg->VtdDisable = 0;
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mainboard_memory_init_params(mupd);
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}
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__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
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