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mb/google/zork: Move PCIE_RST0_L configuration to early GPIO table 

This change moves the configuration of PCIE_RST0_L as native
function to happen in early GPIO table. This ensures that the PERST#
signal is deasserted as soon as possible when the system comes out
of sleep state in case the sleep path asserted/deasserted the PERST#
as GPIO out.

A big difference in functionality with this change is that PCIE_RST0_L
signal is now configured as part of RO, which should be fine since
all PCIe devices have a second AUX_RESET_L signal or use PCIE_RST1_L
to control the actual reset to the device.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I21a9c25b5a8a6d502cdb79cbe0dbad6ef98d6d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2020-06-21 22:27:19 -07:00
parent 8302585c15
commit 2ef3b2df1f
3 changed files with 2 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
View File

@ -13,6 +13,8 @@ static const struct soc_amd_gpio early_gpio_table[] = {
PAD_NF(GPIO_19, I2C3_SCL, PULL_UP),
/* I2C3_SDA - H1 */
PAD_NF(GPIO_20, I2C3_SDA, PULL_UP),
/* PCIE_RST0_L - Fixed timings */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* FCH_ESPI_EC_CS_L */
PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
/* ESPI_ALERT_L (may be unused) */

6
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
View File

@ -15,9 +15,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
/* EC_FCH_WAKE_L */
PAD_GPI(GPIO_24, PULL_UP),
PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
/* PCIE_RST0_L - Fixed timings */
/* TODO: Make sure this gets locked at end of post */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */
@ -52,9 +49,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
/* EC_FCH_WAKE_L */
PAD_GPI(GPIO_24, PULL_UP),
PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
/* PCIE_RST0_L - Fixed timings */
/* TODO: Make sure this gets locked at end of post */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */

6
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
View File

@ -15,9 +15,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
/* EC_FCH_WAKE_L */
PAD_GPI(GPIO_24, PULL_UP),
PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
/* PCIE_RST0_L - Fixed timings */
/* TODO: Make sure this gets locked at end of post */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */
@ -50,9 +47,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
/* EC_FCH_WAKE_L */
PAD_GPI(GPIO_24, PULL_UP),
PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
/* PCIE_RST0_L - Fixed timings */
/* TODO: Make sure this gets locked at end of post */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */