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soc/amd/common/acpi/pci_int.asl: Allow IRQ sharing 

PCI interrupts are level active low, so they can be shared.

BUG=b:184766519
TEST=Boot guybrush to OS with `pci=nomsi amd_iommu=off noapic`

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I439337dd66fe56790406c6d603e73512c806a19d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52957
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Raul E Rangel 2021-05-04 17:01:54 -06:00 committed by Felix Held
parent 6fadde0a53
commit 2f195fe167
1 changed files with 3 additions and 3 deletions
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6
src/soc/amd/common/acpi/pci_int.asl
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@ -2,14 +2,14 @@
/* PIC Possible Resource Values */ /* PIC Possible Resource Values */
Name(IRQP, ResourceTemplate() { Name(IRQP, ResourceTemplate() {
Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , , PIC){ Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , PIC){
1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15
} }
}) })
/* IO-APIC Possible Resource Values */ /* IO-APIC Possible Resource Values */
Name(IRQI, ResourceTemplate() { Name(IRQI, ResourceTemplate() {
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , APIC) { Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , APIC) {
16, 17, 18, 19, 20, 21, 22, 23 16, 17, 18, 19, 20, 21, 22, 23
} }
}) })
@ -63,7 +63,7 @@
ResourceConsumer, \ ResourceConsumer, \
Level, \ Level, \
ActiveLow, \ ActiveLow, \
Exclusive, , , NUMB) \ Shared, , , NUMB) \
{ 0 } \ { 0 } \
} \ } \
CreateDWordField(local0, NUMB._INT, IRQN) \ CreateDWordField(local0, NUMB._INT, IRQN) \