soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC

This patch refactors the current P2SB common code driver to accommodate
the future SoC platform with provision of more than one P2SB IP in
disaggregated die architecture.

IA SoC has only one P2SB in PCH die between SKL to ADL. Starting with
MTL, one more P2SB IP resides in IOE die along with SoC die. (PCH die is
renamed as SoC in MTL.)

P2SB library (p2sblib.c) is common between PCH/SoC and IOE, and p2sb.c
is added only for PCH/SoC P2SB.

BUG=b:224325352
TEST=Able to build and boot brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib671d9acbfdc61305ebb401499bfc4742b738ffb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/common/block/p2sb/Kconfig

@@ -1,5 +1,11 @@
-config SOC_INTEL_COMMON_BLOCK_P2SB
+config SOC_INTEL_COMMON_BLOCK_BASE_P2SB
 	bool
 	depends on SOC_INTEL_COMMON_BLOCK_PCR
 	help
-	  Intel Processor common P2SB driver
+	  Intel Processor common P2SB base driver
+
+config SOC_INTEL_COMMON_BLOCK_P2SB
+	bool
+	select SOC_INTEL_COMMON_BLOCK_BASE_P2SB
+	help
+	  Intel Processor common P2SB driver for PCH or SoC die

src/soc/intel/common/block/p2sb/Makefile.inc

@@ -1,8 +1,8 @@
-ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB),y)
-bootblock-y += p2sb.c
-romstage-y += p2sb.c
-ramstage-y += p2sb.c
-ramstage-y += p2sblib.c
-smm-y += p2sb.c
-smm-y += p2sblib.c
-endif
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c
+
+# p2sb.c for PCH and SoC die P2SB IP
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c