mb/hp/snb_ivb_desktops: Remove superfluous comments about PCI devices
Since all devicetrees from hp/snb_ivb_desktops are using the reference names for PCI devices now, remove the equivalent comments documenting their function. Change-Id: I0974052c6c18f54b588d296c5c5d11e930f0fcd7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80047 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -11,10 +11,10 @@ chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x1791 inherit
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device ref host_bridge on end # Host bridge Host bridge
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device ref peg10 on end # PCIe Bridge for discrete graphics
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device ref igd on end # Internal graphics VGA controller
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device ref peg60 off end # Extra x4 port on north bridge
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device ref host_bridge on end
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device ref peg10 on end
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device ref igd on end
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device ref peg60 off end
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chip southbridge/intel/bd82x6x # Intel Series 7 PCH
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register "docking_supported" = "0"
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@ -29,25 +29,25 @@ chip northbridge/intel/sandybridge
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register "xhci_switchable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x0000000f"
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device ref xhci on end # xHCI
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device ref mei1 on end # Management Engine Interface 1
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device ref mei2 off end # Management Engine Interface 2
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device ref me_ide_r off end # Management Engine IDE-R
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device ref me_kt on end # Management Engine KT
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device ref gbe on end # Intel Gigabit Ethernet
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device ref ehci2 on end # USB2 EHCI #2
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device ref hda on end # High Definition Audio controller
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device ref pcie_rp1 on end # PCIe Port #1
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device ref pcie_rp2 off end # PCIe Port #2
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device ref pcie_rp3 off end # PCIe Port #3
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device ref pcie_rp4 off end # PCIe Port #4
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device ref pcie_rp5 on end # PCIe Port #5
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device ref pcie_rp6 off end # PCIe Port #6
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device ref pcie_rp7 off end # PCIe Port #7
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device ref pcie_rp8 off end # PCIe Port #8
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device ref ehci1 on end # USB2 EHCI #1
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device ref pci_bridge on end # PCI bridge
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device ref lpc on # LPC bridge PCI-LPC bridge
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device ref xhci on end
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device ref mei1 on end
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device ref mei2 off end
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device ref me_ide_r off end
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device ref me_kt on end
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device ref gbe on end
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device ref ehci2 on end
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device ref hda on end
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device ref pcie_rp1 on end
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device ref pcie_rp2 off end
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device ref pcie_rp3 off end
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device ref pcie_rp4 off end
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device ref pcie_rp5 on end
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device ref pcie_rp6 off end
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device ref pcie_rp7 off end
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device ref pcie_rp8 off end
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device ref ehci1 on end
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device ref pci_bridge on end
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device ref lpc on
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chip superio/common
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device pnp 2e.ff on # passes SIO base addr to SSDT gen
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chip superio/nuvoton/npcd378
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@ -152,10 +152,10 @@ chip northbridge/intel/sandybridge
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device pnp 4e.0 on end # TPM module
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end
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end
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device ref sata1 on end # SATA Controller 1
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device ref smbus on end # SMBus
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device ref sata2 off end # SATA Controller 2
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device ref thermal off end # Thermal
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device ref sata1 on end
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device ref smbus on end
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device ref sata2 off end
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device ref thermal off end
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end
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end
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end
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@ -3,16 +3,16 @@
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chip northbridge/intel/sandybridge
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device domain 0 on
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subsystemid 0x103c 0x1791 inherit
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device ref peg60 on end # Extra x4 port on north bridge
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device ref peg60 on end
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chip southbridge/intel/bd82x6x
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register "sata_port_map" = "0x3f"
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device ref pcie_rp2 on end # PCIe Port #2
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device ref pcie_rp3 on end # PCIe Port #3
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device ref pcie_rp4 on end # PCIe Port #4
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device ref pcie_rp6 on end # PCIe Port #6
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device ref pcie_rp7 on end # PCIe Port #7
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device ref pcie_rp8 on end # PCIe Port #8
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device ref pcie_rp2 on end
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device ref pcie_rp3 on end
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device ref pcie_rp4 on end
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device ref pcie_rp6 on end
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device ref pcie_rp7 on end
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device ref pcie_rp8 on end
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end
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end
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end
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