ARMv7: drop __ASSEMBLY__
We moved to using __ASSEMBLER__ years ago since it is set by as. Change-Id: I60103ba23ebe87be1d0bc63beed0ef5b05eed4f2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2111 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
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2f25d9963e
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@ -60,7 +60,7 @@
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#define arch_align_stack(x) (x)
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#define arch_align_stack(x) (x)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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static inline unsigned int get_cr(void)
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static inline unsigned int get_cr(void)
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{
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{
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unsigned int val;
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unsigned int val;
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@ -29,7 +29,6 @@
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* MA 02111-1307 USA
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* MA 02111-1307 USA
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*/
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*/
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#define __ASSEMBLY__
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#include <system.h>
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#include <system.h>
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.globl _start
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.globl _start
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@ -29,7 +29,6 @@
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* MA 02111-1307 USA
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* MA 02111-1307 USA
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*/
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*/
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#define __ASSEMBLY__
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#include <system.h>
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#include <system.h>
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.globl _start
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.globl _start
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@ -25,7 +25,7 @@
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#ifndef __ASM_ARM_ARCH_COMMON_ADC_H_
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#ifndef __ASM_ARM_ARCH_COMMON_ADC_H_
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#define __ASM_ARM_ARCH_COMMON_ADC_H_
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#define __ASM_ARM_ARCH_COMMON_ADC_H_
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5p_adc {
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struct s5p_adc {
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unsigned int adccon;
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unsigned int adccon;
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unsigned int adctsc;
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unsigned int adctsc;
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@ -21,7 +21,7 @@
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#ifndef __ASM_ARCH_COMMON_GPIO_H
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#ifndef __ASM_ARCH_COMMON_GPIO_H
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#define __ASM_ARCH_COMMON_GPIO_H
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#define __ASM_ARCH_COMMON_GPIO_H
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#ifndef __ASSEMBLY__ /* FIXME: not needed (i hope)? */
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#ifndef __ASSEMBLER__ /* FIXME: not needed (i hope)? */
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#include <cpu/samsung/s5p-common/gpio.h>
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#include <cpu/samsung/s5p-common/gpio.h>
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/* FIXME: s5p's gpio.h and exynos' gpio.h have a lot of conflicting
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/* FIXME: s5p's gpio.h and exynos' gpio.h have a lot of conflicting
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definitions */
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definitions */
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@ -21,7 +21,7 @@
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#ifndef __ASM_ARCH_COMMON_MMC_H_
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#ifndef __ASM_ARCH_COMMON_MMC_H_
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#define __ASM_ARCH_COMMON_MMC_H_
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#define __ASM_ARCH_COMMON_MMC_H_
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5p_mmc {
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struct s5p_mmc {
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unsigned int sysad;
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unsigned int sysad;
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unsigned short blksize;
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unsigned short blksize;
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@ -73,5 +73,5 @@ int s5p_mmc_init(const void *blob);
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int s5p_mmc_init(int dev_index, int bus_width);
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int s5p_mmc_init(int dev_index, int bus_width);
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#endif
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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#endif
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#endif
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@ -21,7 +21,7 @@
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#define __ASM_ARCH_COMMON_MSHC_H
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#define __ASM_ARCH_COMMON_MSHC_H
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pinmux.h>
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct mshci_host {
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struct mshci_host {
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struct s5p_mshci *reg; /* Mapped address */
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struct s5p_mshci *reg; /* Mapped address */
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unsigned int clock; /* Current clock in MHz */
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unsigned int clock; /* Current clock in MHz */
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@ -42,7 +42,7 @@
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#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
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#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
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#define TCON4_AUTO_RELOAD (1 << 22)
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#define TCON4_AUTO_RELOAD (1 << 22)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5p_timer {
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struct s5p_timer {
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unsigned int tcfg0;
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unsigned int tcfg0;
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unsigned int tcfg1;
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unsigned int tcfg1;
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@ -63,6 +63,6 @@ struct s5p_timer {
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unsigned int tcnto4;
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unsigned int tcnto4;
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unsigned int tintcstat;
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unsigned int tintcstat;
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};
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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#endif
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#endif
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@ -20,7 +20,7 @@
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#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
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#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
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#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
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#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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/* SPI peripheral register map; padded to 64KB */
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/* SPI peripheral register map; padded to 64KB */
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struct exynos_spi {
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struct exynos_spi {
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@ -85,5 +85,5 @@ struct exynos_spi {
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#define SPI_RX_BYTE_SWAP (1 << 6)
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#define SPI_RX_BYTE_SWAP (1 << 6)
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#define SPI_RX_HWORD_SWAP (1 << 7)
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#define SPI_RX_HWORD_SWAP (1 << 7)
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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#endif
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#endif
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@ -38,12 +38,12 @@
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#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
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#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
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#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
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#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5p_sromc {
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struct s5p_sromc {
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unsigned int bw;
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unsigned int bw;
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unsigned int bc[4];
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unsigned int bc[4];
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};
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
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/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
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void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
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void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
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@ -41,7 +41,7 @@
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#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
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#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
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#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
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#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5p_watchdog {
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struct s5p_watchdog {
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unsigned int wtcon;
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unsigned int wtcon;
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unsigned int wtdat;
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unsigned int wtdat;
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@ -52,6 +52,6 @@ struct s5p_watchdog {
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/* functions */
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/* functions */
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void wdt_stop(void);
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void wdt_stop(void);
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void wdt_start(unsigned int timeout);
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void wdt_start(unsigned int timeout);
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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#endif
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#endif
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@ -79,7 +79,7 @@
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/* Distance between each Trust Zone PC register set */
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/* Distance between each Trust Zone PC register set */
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#define TZPC_BASE_OFFSET 0x10000
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#define TZPC_BASE_OFFSET 0x10000
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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#define SAMSUNG_BASE(device, base) \
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#define SAMSUNG_BASE(device, base) \
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static inline unsigned int samsung_get_base_##device(void) \
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static inline unsigned int samsung_get_base_##device(void) \
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#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
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#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
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#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
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#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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/* SPI peripheral register map; padded to 64KB */
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/* SPI peripheral register map; padded to 64KB */
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struct exynos_spi {
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struct exynos_spi {
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#define SPI_RX_BYTE_SWAP (1 << 6)
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#define SPI_RX_BYTE_SWAP (1 << 6)
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#define SPI_RX_HWORD_SWAP (1 << 7)
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#define SPI_RX_HWORD_SWAP (1 << 7)
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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#endif
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#endif
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#ifndef __ASM_ARM_ARCH_CLOCK_H_
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#ifndef __ASM_ARM_ARCH_CLOCK_H_
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#define __ASM_ARM_ARCH_CLOCK_H_
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#define __ASM_ARM_ARCH_CLOCK_H_
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5pc100_clock {
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struct s5pc100_clock {
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unsigned int apll_lock;
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unsigned int apll_lock;
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unsigned int mpll_lock;
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unsigned int mpll_lock;
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#include <cpu/samsung/s5p-common/cpu.h> /* FIXME: for S5PC110_GPIO_BASE */
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#include <cpu/samsung/s5p-common/cpu.h> /* FIXME: for S5PC110_GPIO_BASE */
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5p_gpio_bank {
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struct s5p_gpio_bank {
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unsigned int con;
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unsigned int con;
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unsigned int dat;
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unsigned int dat;
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#ifndef __ASM_ARCH_MMC_H_
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#ifndef __ASM_ARCH_MMC_H_
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#define __ASM_ARCH_MMC_H_
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#define __ASM_ARCH_MMC_H_
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5p_mmc {
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struct s5p_mmc {
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unsigned int sysad;
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unsigned int sysad;
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unsigned short blksize;
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unsigned short blksize;
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int s5p_mmc_init(int dev_index, int bus_width);
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int s5p_mmc_init(int dev_index, int bus_width);
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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#endif
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#endif
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#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
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#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
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#define TCON4_AUTO_RELOAD (1 << 22)
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#define TCON4_AUTO_RELOAD (1 << 22)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5p_timer {
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struct s5p_timer {
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unsigned int tcfg0;
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unsigned int tcfg0;
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unsigned int tcfg1;
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unsigned int tcfg1;
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unsigned int tcnto4;
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unsigned int tcnto4;
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unsigned int tintcstat;
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unsigned int tintcstat;
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};
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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/* FIXME(dhendrix): added missing prototypes... */
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/* FIXME(dhendrix): added missing prototypes... */
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int pwm_config(int pwm_id, int duty_ns, int period_ns);
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int pwm_config(int pwm_id, int duty_ns, int period_ns);
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#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
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#define SMC_BC_TACP(x) (x << 4) /* 6clk page mode access cycle */
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#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
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#define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5p_sromc {
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struct s5p_sromc {
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unsigned int bw;
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unsigned int bw;
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unsigned int bc[6];
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unsigned int bc[6];
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};
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
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/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
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void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
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void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
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#ifndef __ASM_ARCH_UART_H_
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#ifndef __ASM_ARCH_UART_H_
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#define __ASM_ARCH_UART_H_
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#define __ASM_ARCH_UART_H_
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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/* baudrate rest value */
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/* baudrate rest value */
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union br_rest {
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union br_rest {
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unsigned short slot; /* udivslot */
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unsigned short slot; /* udivslot */
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return 1;
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return 1;
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}
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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#endif
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#endif
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#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
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#define WTCON_RESET (0x1 << WTCON_RESET_OFFSET)
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#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
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#define WTCON_INT (0x1 << WTCON_INTEN_OFFSET)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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struct s5p_watchdog {
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struct s5p_watchdog {
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unsigned int wtcon;
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unsigned int wtcon;
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unsigned int wtdat;
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unsigned int wtdat;
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/* functions */
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/* functions */
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void wdt_stop(void);
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void wdt_stop(void);
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void wdt_start(unsigned int timeout);
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void wdt_start(unsigned int timeout);
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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#endif
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#endif
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