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nb/intel/gm45: Clean up header handling 

There's no need to have ACPI guards in `gm45.h`, since the only things
the ASL files require are the base address definitions in `memmap.h`.
Also, remove the southbridge include from `gm45.h` and place it only in
the files that actually require something from it.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: Ica2c5ae9f57595c8577a1bfcc3b57f2c57b3e980
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45452
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-09-16 13:29:21 +02:00
parent ae2a522827
commit 2f30e8ca03
4 changed files with 4 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/northbridge/intel/gm45/acpi/gm45.asl
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@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include "hostbridge.asl" #include "hostbridge.asl"
#include "../gm45.h" #include "../memmap.h"
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <southbridge/intel/common/rcba.h> #include <southbridge/intel/common/rcba.h>
/* PCI Device Resource Consumption */ /* PCI Device Resource Consumption */

1
src/northbridge/intel/gm45/early_init.c
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@ -2,6 +2,7 @@
#include <stdint.h> #include <stdint.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include "gm45.h" #include "gm45.h"
void gm45_early_init(void) void gm45_early_init(void)

9
src/northbridge/intel/gm45/gm45.h
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@ -3,10 +3,6 @@
#ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__
#define __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__
#include <southbridge/intel/i82801ix/i82801ix.h>
#ifndef __ACPI__
#include <stdint.h> #include <stdint.h>
typedef enum { typedef enum {
@ -163,8 +159,6 @@ enum {
VCO_5333 = 2, VCO_5333 = 2,
}; };
#endif
/* Offsets of read/write training results in CMOS. /* Offsets of read/write training results in CMOS.
They will be restored upon S3 resumes. */ They will be restored upon S3 resumes. */
#define CMOS_READ_TRAINING 0x80 /* 16 bytes */ #define CMOS_READ_TRAINING 0x80 /* 16 bytes */
@ -409,8 +403,6 @@ enum {
#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ #define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */
#ifndef __ACPI__
void gm45_early_init(void); void gm45_early_init(void);
void gm45_early_reset(void); void gm45_early_reset(void);
@ -460,5 +452,4 @@ struct acpi_rsdp;
unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start,
struct acpi_rsdp *rsdp); struct acpi_rsdp *rsdp);
#endif /* !__ACPI__ */
#endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */

1
src/northbridge/intel/gm45/pcie.c
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@ -4,6 +4,7 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <console/console.h> #include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include "gm45.h" #include "gm45.h"