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google/link: implement get_write_protect_state 

Current vboot wants that function.

Change-Id: I9d3a592c448cf2af10f76cae4518341cbc0a6f41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2015-06-30 12:49:50 +02:00 committed by Stefan Reinauer
parent 94b8ad4879
commit 2f31ef1115
1 changed files with 20 additions and 10 deletions
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30
src/mainboard/google/link/chromeos.c
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@ -33,22 +33,13 @@
void fill_lb_gpios(struct lb_gpios *gpios)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
//u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
if (!gpio_base)
return;
u32 gp_lvl2 = inl(gpio_base + 0x38);
gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
gpios->count = GPIO_COUNT;
/* Write Protect: GPIO57 = PCH_SPI_WP_D */
gpios->gpios[0].port = 57;
gpios->gpios[0].polarity = ACTIVE_HIGH;
gpios->gpios[0].value = (gp_lvl2 >> (57 - 32)) & 1;
gpios->gpios[0].value = get_write_protect_state();
strncpy((char *)gpios->gpios[0].name,"write protect",
GPIO_MAX_NAME_LENGTH);
/* Recovery: the "switch" comes from the EC */
@ -84,6 +75,25 @@ void fill_lb_gpios(struct lb_gpios *gpios)
}
#endif
int get_write_protect_state(void)
{
device_t dev;
#ifdef __PRE_RAM__
dev = PCI_DEV(0, 0x1f, 0);
#else
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
#endif
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
//u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
if (!gpio_base)
return -1;
u32 gp_lvl2 = inl(gpio_base + 0x38);
return (gp_lvl2 >> (57 - 32)) & 1;
}
int get_lid_switch(void)
{
u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);