mb/google/hatch/var/akemi: tune DPTF for Akemi
Tune DPTF to ensure compliance with Akemi thermal design requirements BUG=b:144195069 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ie0e6d93e1fc0c684e067d1450eb119a53cfefaed Reviewed-on: https://review.coreboot.org/c/coreboot/+/36716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Peichao Wang
Patrick Georgi
parent
6b9cff49b0
commit
2f35744e40
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@ -25,33 +25,33 @@
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#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1"
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#define DPTF_TSR0_PASSIVE 65
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#define DPTF_TSR0_CRITICAL 75
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#define DPTF_TSR0_ACTIVE_AC0 50
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#define DPTF_TSR0_ACTIVE_AC1 47
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#define DPTF_TSR0_ACTIVE_AC2 45
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#define DPTF_TSR0_ACTIVE_AC3 42
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#define DPTF_TSR0_ACTIVE_AC4 39
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#define DPTF_TSR0_ACTIVE_AC0 61
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#define DPTF_TSR0_ACTIVE_AC1 59
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#define DPTF_TSR0_ACTIVE_AC2 57
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#define DPTF_TSR0_ACTIVE_AC3 55
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#define DPTF_TSR0_ACTIVE_AC4 51
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#define DPTF_TSR0_ACTIVE_AC5 48
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#define DPTF_TSR0_ACTIVE_AC6 40
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#define DPTF_TSR1_SENSOR_ID 1
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#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2"
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#define DPTF_TSR1_PASSIVE 65
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#define DPTF_TSR1_PASSIVE 38
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#define DPTF_TSR1_CRITICAL 75
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#define DPTF_TSR1_ACTIVE_AC0 50
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#define DPTF_TSR1_ACTIVE_AC1 47
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#define DPTF_TSR1_ACTIVE_AC2 45
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#define DPTF_TSR1_ACTIVE_AC3 42
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#define DPTF_TSR1_ACTIVE_AC4 39
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#define DPTF_TSR1_ACTIVE_AC0 42
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#define DPTF_TSR1_ACTIVE_AC1 40
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#define DPTF_TSR1_ACTIVE_AC2 38
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#define DPTF_TSR2_SENSOR_ID 2
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#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU"
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#define DPTF_TSR2_PASSIVE 60
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#define DPTF_TSR2_CRITICAL 75
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#define DPTF_TSR2_ACTIVE_AC0 51
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#define DPTF_TSR2_ACTIVE_AC1 48
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#define DPTF_TSR2_ACTIVE_AC2 45
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#define DPTF_TSR2_ACTIVE_AC3 42
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#define DPTF_TSR2_ACTIVE_AC4 39
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#define DPTF_TSR2_ACTIVE_AC5 36
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#define DPTF_TSR2_ACTIVE_AC6 33
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#define DPTF_TSR2_PASSIVE 62
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#define DPTF_TSR2_CRITICAL 105
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#define DPTF_TSR2_ACTIVE_AC0 62
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#define DPTF_TSR2_ACTIVE_AC1 61
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#define DPTF_TSR2_ACTIVE_AC2 60
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#define DPTF_TSR2_ACTIVE_AC3 54
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#define DPTF_TSR2_ACTIVE_AC4 51
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#define DPTF_TSR2_ACTIVE_AC5 48
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#define DPTF_TSR2_ACTIVE_AC6 45
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#define DPTF_ENABLE_CHARGER
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#define DPTF_ENABLE_FAN_CONTROL
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@ -72,16 +72,21 @@ Name (DFPS, Package () {
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* These are initial reference values.
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*/
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/* Control, Trip Point, Speed, NoiseLevel, Power */
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Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
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Package () {80, 0xFFFFFFFF, 5800, 180, 1800},
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Package () {70, 0xFFFFFFFF, 5000, 145, 1450},
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Package () {60, 0xFFFFFFFF, 4900, 115, 1150},
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Package () {50, 0xFFFFFFFF, 3838, 90, 900},
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Package () {40, 0xFFFFFFFF, 2904, 55, 550},
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Package () {30, 0xFFFFFFFF, 2337, 30, 300},
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Package () {20, 0xFFFFFFFF, 1608, 15, 150},
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Package () {10, 0xFFFFFFFF, 800, 10, 100},
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Package () {0, 0xFFFFFFFF, 0, 0, 50}
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Package () {85, 0xFFFFFFFF, 5500, 180, 1800},
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Package () {79, 0xFFFFFFFF, 5400, 170, 1700},
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Package () {73, 0xFFFFFFFF, 5200, 160, 1600},
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Package () {68, 0xFFFFFFFF, 5000, 150, 1500},
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Package () {62, 0xFFFFFFFF, 4800, 140, 1400},
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Package () {58, 0xFFFFFFFF, 4600, 130, 1300},
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Package () {53, 0xFFFFFFFF, 4400, 110, 1100},
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Package () {49, 0xFFFFFFFF, 4200, 95, 950},
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Package () {46, 0xFFFFFFFF, 4000, 70, 700},
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Package () {42, 0xFFFFFFFF, 3700, 50, 500},
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Package () {40, 0xFFFFFFFF, 3600, 35, 350},
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Package () {36, 0xFFFFFFFF, 3400, 25, 250},
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Package () {33, 0xFFFFFFFF, 3200, 15, 150},
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Package () {30, 0xFFFFFFFF, 3000, 5, 50},
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Package () {0, 0xFFFFFFFF, 0, 0, 0}
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})
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Name (DART, Package () {
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@ -96,15 +101,15 @@ Name (DART, Package () {
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 85, 73, 62, 49, 33, 25, 14,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 85, 73, 62, 0, 0, 0, 0,
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0, 0, 0
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},
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Package () {
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 80, 70, 60, 50, 40, 30,
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\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 85, 73, 62, 56, 33, 25, 14,
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0, 0, 0
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},
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})
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@ -114,13 +119,13 @@ Name (DTRT, Package () {
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Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
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/* CPU Throttle Effect on Ambient (TSR0) */
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
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Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
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/* Charger Throttle Effect on Charger (TSR1) */
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Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
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/* CPU Throttle Effect on CPU (TSR2) */
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Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
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Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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@ -128,7 +133,7 @@ Name (MPPC, Package ()
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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3000, /* PowerLimitMinimum */
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5000, /* PowerLimitMinimum */
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15000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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32000, /* TimeWindowMaximum */
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