nb/intel/sandybridge: Reduce the scope of get_CWL()

It is only used once, and can thus be moved to the same file.

Change-Id: I4ee0621449da7fa1970a475d5a2f6e66546357ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons 2020-11-11 18:49:31 +01:00 committed by Patrick Georgi
parent 765d465a23
commit 2f3cc0035d
3 changed files with 35 additions and 36 deletions

View File

@ -80,41 +80,6 @@ static u32 get_XOVER_CMD(u8 rankmap)
return reg; return reg;
} }
/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */
u8 get_CWL(u32 tCK)
{
/* Get CWL based on tCK using the following rule */
switch (tCK) {
case TCK_1333MHZ:
return 12;
case TCK_1200MHZ:
case TCK_1100MHZ:
return 11;
case TCK_1066MHZ:
case TCK_1000MHZ:
return 10;
case TCK_933MHZ:
case TCK_900MHZ:
return 9;
case TCK_800MHZ:
case TCK_700MHZ:
return 8;
case TCK_666MHZ:
return 7;
case TCK_533MHZ:
return 6;
default:
return 5;
}
}
void dram_find_common_params(ramctr_timing *ctrl) void dram_find_common_params(ramctr_timing *ctrl)
{ {
size_t valid_dimms; size_t valid_dimms;

View File

@ -227,7 +227,6 @@ typedef struct ramctr_timing_st {
#define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1) #define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1)
#define GET_ERR_CHANNEL(x) (x >> 16) #define GET_ERR_CHANNEL(x) (x >> 16)
u8 get_CWL(u32 tCK);
void dram_mrscommands(ramctr_timing *ctrl); void dram_mrscommands(ramctr_timing *ctrl);
void program_timings(ramctr_timing *ctrl, int channel); void program_timings(ramctr_timing *ctrl, int channel);
void dram_find_common_params(ramctr_timing *ctrl); void dram_find_common_params(ramctr_timing *ctrl);

View File

@ -42,6 +42,41 @@ static u32 get_FRQ(const ramctr_timing *ctrl)
die("Unsupported CPU or base frequency."); die("Unsupported CPU or base frequency.");
} }
/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */
static u8 get_CWL(u32 tCK)
{
/* Get CWL based on tCK using the following rule */
switch (tCK) {
case TCK_1333MHZ:
return 12;
case TCK_1200MHZ:
case TCK_1100MHZ:
return 11;
case TCK_1066MHZ:
case TCK_1000MHZ:
return 10;
case TCK_933MHZ:
case TCK_900MHZ:
return 9;
case TCK_800MHZ:
case TCK_700MHZ:
return 8;
case TCK_666MHZ:
return 7;
case TCK_533MHZ:
return 6;
default:
return 5;
}
}
/* Get REFI based on frequency index, tREFI = 7.8usec */ /* Get REFI based on frequency index, tREFI = 7.8usec */
static u32 get_REFI(u32 FRQ, u8 base_freq) static u32 get_REFI(u32 FRQ, u8 base_freq)
{ {