nb/intel/sandybridge: Reduce the scope of get_CWL()
It is only used once, and can thus be moved to the same file. Change-Id: I4ee0621449da7fa1970a475d5a2f6e66546357ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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@ -80,41 +80,6 @@ static u32 get_XOVER_CMD(u8 rankmap)
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return reg;
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}
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/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */
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u8 get_CWL(u32 tCK)
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{
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/* Get CWL based on tCK using the following rule */
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switch (tCK) {
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case TCK_1333MHZ:
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return 12;
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case TCK_1200MHZ:
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case TCK_1100MHZ:
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return 11;
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case TCK_1066MHZ:
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case TCK_1000MHZ:
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return 10;
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case TCK_933MHZ:
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case TCK_900MHZ:
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return 9;
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case TCK_800MHZ:
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case TCK_700MHZ:
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return 8;
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case TCK_666MHZ:
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return 7;
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case TCK_533MHZ:
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return 6;
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default:
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return 5;
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}
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}
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void dram_find_common_params(ramctr_timing *ctrl)
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{
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size_t valid_dimms;
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@ -227,7 +227,6 @@ typedef struct ramctr_timing_st {
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#define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1)
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#define GET_ERR_CHANNEL(x) (x >> 16)
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u8 get_CWL(u32 tCK);
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void dram_mrscommands(ramctr_timing *ctrl);
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void program_timings(ramctr_timing *ctrl, int channel);
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void dram_find_common_params(ramctr_timing *ctrl);
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@ -42,6 +42,41 @@ static u32 get_FRQ(const ramctr_timing *ctrl)
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die("Unsupported CPU or base frequency.");
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}
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/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */
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static u8 get_CWL(u32 tCK)
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{
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/* Get CWL based on tCK using the following rule */
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switch (tCK) {
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case TCK_1333MHZ:
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return 12;
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case TCK_1200MHZ:
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case TCK_1100MHZ:
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return 11;
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case TCK_1066MHZ:
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case TCK_1000MHZ:
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return 10;
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case TCK_933MHZ:
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case TCK_900MHZ:
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return 9;
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case TCK_800MHZ:
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case TCK_700MHZ:
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return 8;
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case TCK_666MHZ:
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return 7;
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case TCK_533MHZ:
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return 6;
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default:
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return 5;
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}
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}
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/* Get REFI based on frequency index, tREFI = 7.8usec */
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static u32 get_REFI(u32 FRQ, u8 base_freq)
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{
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