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exynos5420: Alter init sequence as per recommendation 

As per hardware recommendation, CKE PAD retention release must
happen just before gate leveling enable and only in case of resume.
Hence, this patch moves pad retention release from dmc_common.c to
dmc_init_ddr3_exynos5420.c. In addition to this we are providing
125 (+3 extra being safe) times auto refresh to DRAM by sending
REFA direct command. This is required because when CKE PAD retention
release happens, self refresh mode of DDR3 is disabled.
Hence, auto refresh 125 times.

This is ported from https://gerrit.chromium.org/gerrit/#/c/65573

Note: Since WAKEUP_DIRECT does not go thru memory init, it should be
safe to move CKE PAD retention out of bootblock.c.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Idec5d6fbbe3c6344d47401ba7203079c52a9b866
Reviewed-on: https://gerrit.chromium.org/gerrit/66788
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 96cbcb09245d4df92d3e1998704ab440be42df25)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6604
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
David Hendricks 2013-08-20 17:13:01 -07:00 committed by Isaac Christensen
parent ad4556f2cb
commit 2f3daddd28
3 changed files with 35 additions and 22 deletions
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17
src/cpu/samsung/exynos5420/bootblock.c
View File

@ -31,23 +31,6 @@
void bootblock_cpu_init(void);
void bootblock_cpu_init(void)
{
u32 ret;
/*
* During Suspend-Resume & S/W-Reset, as soon as PMU releases
* pad retention, CKE goes high. This causes memory contents
* not to be retained during DRAM initialization. Therfore,
* there is a new control register(0x100431e8[28]) which lets us
* release pad retention and retain the memory content until the
* initialization is complete.
*/
if (read32(((void *)INF_REG_BASE + INF_REG1_OFFSET)) == S5P_CHECK_SLEEP) {
write32(PAD_RETENTION_DRAM_COREBLK_VAL,
(void *)PAD_RETENTION_DRAM_COREBLK_OPTION);
do {
ret = read32((void *)PAD_RETENTION_DRAM_STATUS);
} while (ret != 0x1);
}
/* kick off the multi-core timer.
* We want to do this as early as we can.
*/

39
src/cpu/samsung/exynos5420/dmc_init_ddr3.c
View File

@ -184,14 +184,43 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(mem->timing_power, &drex0->timingpower);
writel(mem->timing_power, &drex1->timingpower);
/* Send NOP, MRS and ZQINIT commands.
* Sending MRS command will reset the DRAM. We should not be
* reseting the DRAM after resume, this will lead to memory
* corruption as DRAM content is lost after DRAM reset.
*/
if (reset) {
/* Send NOP, MRS and ZQINIT commands.
* Sending MRS command will reset the DRAM. We should not be
* reseting the DRAM after resume, this will lead to memory
* corruption as DRAM content is lost after DRAM reset.
*/
dmc_config_mrs(mem, drex0);
dmc_config_mrs(mem, drex1);
} else {
u32 ret;
/*
* During Suspend-Resume & S/W-Reset, as soon as PMU releases
* pad retention, CKE goes high. This causes memory contents
* not to be retained during DRAM initialization. Therfore,
* there is a new control register(0x100431e8[28]) which lets us
* release pad retention and retain the memory content until the
* initialization is complete.
*/
write32(PAD_RETENTION_DRAM_COREBLK_VAL,
(void *)PAD_RETENTION_DRAM_COREBLK_OPTION);
do {
ret = read32((void *)PAD_RETENTION_DRAM_STATUS);
} while (ret != 0x1);
/*
* CKE PAD retention disables DRAM self-refresh mode.
* Send auto refresh command for DRAM refresh.
*/
for (i = 0; i < 128; i++) {
writel(DIRECT_CMD_REFA, &drex0->directcmd);
writel(DIRECT_CMD_REFA | (0x1 << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(DIRECT_CMD_REFA, &drex1->directcmd);
writel(DIRECT_CMD_REFA | (0x1 << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
}
if (mem->gate_leveling_enable) {

1
src/cpu/samsung/exynos5420/setup.h
View File

@ -715,6 +715,7 @@ struct exynos5_phy_control;
#define DIRECT_CMD_ZQINIT 0x0a000000
#define DIRECT_CMD_CHANNEL_SHIFT 28
#define DIRECT_CMD_CHIP_SHIFT 20
#define DIRECT_CMD_BANK_SHIFT 16
#define DIRECT_CMD_REFA (5 << 24)
#define DIRECT_CMD_MRS1 0x71C00
#define DIRECT_CMD_MRS2 0x10BFC