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sb/pi/hudson: Const'ify pci_devfn_t devices 

Change-Id: I9e63c811c4ac5674b2930304455d828ee516b521
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Elyes HAOUAS 2020-04-22 16:07:39 +02:00 committed by Michał Żygowski
parent db4f3bacce
commit 2f58a007a7
2 changed files with 8 additions and 13 deletions
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7
src/southbridge/amd/pi/hudson/bootblock.c
View File

@ -19,9 +19,7 @@
static void hudson_enable_rom(void)
{
u8 reg8;
pci_devfn_t dev;
dev = PCI_DEV(0, 0x14, 3);
const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
/* Decode variable LPC ROM address ranges 1 and 2. */
reg8 = pci_s_read_config8(dev, 0x48);
@ -49,7 +47,6 @@ static void hudson_enable_rom(void)
void bootblock_early_southbridge_init(void)
{
pci_devfn_t dev;
u32 data;
hudson_enable_rom();
@ -64,7 +61,7 @@ void bootblock_early_southbridge_init(void)
else if (CONFIG(POST_DEVICE_LPC))
hudson_lpc_port80();
dev = PCI_DEV(0, 0x14, 3);
const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
/* enable 0x2e/0x4e IO decoding for SuperIO */
pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);

14
src/southbridge/amd/pi/hudson/early_setup.c
View File

@ -92,10 +92,9 @@ void hudson_pci_port80(void)
void hudson_lpc_port80(void)
{
u8 byte;
pci_devfn_t dev;
/* Enable port 80 LPC decode in pci function 3 configuration space. */
dev = PCI_DEV(0, 0x14, 3);
const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
byte = pci_read_config8(dev, 0x4a);
byte |= 1 << 5; /* enable port 80 */
pci_write_config8(dev, 0x4a, byte);
@ -103,13 +102,12 @@ void hudson_lpc_port80(void)
void hudson_lpc_decode(void)
{
pci_devfn_t dev;
u32 tmp;
/* Enable LPC controller */
pm_write8(0xec, pm_read8(0xec) | 0x01);
dev = PCI_DEV(0, 0x14, 3);
const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
/* Serial port numeration on Hudson:
* PORT0 - 0x3f8
* PORT1 - 0x2f8
@ -134,7 +132,7 @@ static void enable_wideio(uint8_t port, uint16_t size)
LPC_ALT_WIDEIO1_ENABLE,
LPC_ALT_WIDEIO2_ENABLE
};
pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
const pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
uint32_t tmp;
/* Only allow port 0-2 */
@ -168,7 +166,7 @@ static void enable_wideio(uint8_t port, uint16_t size)
*/
static void lpc_wideio_window(uint16_t base, uint16_t size)
{
pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
const pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
u32 tmp;
/* Support 512 or 16 bytes per range */
@ -227,7 +225,7 @@ void hudson_clk_output_48Mhz(void)
static uintptr_t hudson_spibase(void)
{
/* Make sure the base address is predictable */
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER)
& 0xfffffff0;
@ -280,7 +278,7 @@ void hudson_read_mode(u32 mode)
void hudson_tpm_decode_spi(void)
{
pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */
const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); /* LPC device */
u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase