soc/intel/denverton_ns: Enable Fast Strings

Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25431
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/denverton_ns/cpu.c

@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2015 - 2017 Intel Corp.
+ * Copyright (C) 2018 Online SAS
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -39,6 +40,11 @@ static void denverton_core_init(struct device *cpu)
 
 	printk(BIOS_DEBUG, "Init Denverton-NS SoC cores.\n");
 
+	/* Enable Fast Strings */
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo |= FAST_STRINGS_ENABLE_BIT;
+	wrmsr(IA32_MISC_ENABLE, msr);
+
 	/* Enable Turbo */
 	enable_turbo();
 

src/soc/intel/denverton_ns/include/soc/msr.h

@@ -92,6 +92,7 @@
 #define PRMRR_SUPPORTED (1 << 12)
 
 /* IA32_MISC_ENABLE bits */
+#define FAST_STRINGS_ENABLE_BIT (1 << 0)
 #define SPEED_STEP_ENABLE_BIT (1 << 16)
 
 /* Read BCLK from MSR */