updated for v2
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -1,7 +1,21 @@
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##
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## CPU initialization
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##
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initinclude "EARLY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
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uses _RAMBASE
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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##
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## Use cache ram for initial setup
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##
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default USE_DCACHE_RAM=1
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## Set dcache ram above linuxbios image
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default DCACHE_RAM_BASE=_RAMBASE+0x100000
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## Dcache size is 16Kb
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default DCACHE_RAM_SIZE=16384
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initinclude "FAMILY_INIT" cpu/ppc/mpc74xx/mpc74xx.inc
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object clock.o
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initobject clock.o
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@ -89,13 +89,6 @@
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mtsr 15, r0
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isync
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/*
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* Initialize northbridge. This has to happen early because it
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* resets memory. Memory is on at this point, albeit with
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* pessimistic settings. We reconfigure later using I2C.
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*/
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bl bsp_init_northbridge
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/*
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* Set up DBATs
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*
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@ -183,8 +176,3 @@ tlblp:
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ori r2, r2, HID0_ICE | HID0_ICFI
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isync
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mtspr HID0, r2
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/*
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* Must branch to start_payload once CPU initialization is completed
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*/
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b start_payload
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