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mb/google/kahlee/treeya: tune eDP delay time to 20 ms 

tune eDP delay time to 20 ms ensure satisfy panel spec

BUG=b:147270512
TEST=verify panel sequences by ODM.

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ia38fbcb976de55baae480d33c6000c91dc9de6bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38024
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Peichao Wang 2019-12-31 11:24:13 +08:00 committed by Martin Roth
parent e938fb78f9
commit 2f72a204a7
1 changed files with 2 additions and 0 deletions
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src/mainboard/google/kahlee/variants/treeya/devicetree.cb
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@ -23,6 +23,8 @@ chip soc/amd/stoneyridge
register "stapm_percent" = "68"
register "stapm_time_ms" = "900000"
register "stapm_power_mw" = "7800"
register "lvds_poseq_varybl_to_blon" = "0x5"
register "lvds_poseq_blon_to_varybl" = "0x5"
# Enable I2C0 for audio, USB3 hub at 400kHz
register "i2c[0]" = "{