arch/riscv: Visually align trap frame information
The pointers printed on unaligned memory accesses are now aligned to those printed at the end of print_trap_information. Change-Id: Ifec1cb639036ce61b81fe8d0a9b14c00d5b2781a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16983 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -172,8 +172,8 @@ static uint32_t fetch_instruction(uintptr_t vaddr) {
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}
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}
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void handle_misaligned_load(trapframe *tf) {
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void handle_misaligned_load(trapframe *tf) {
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printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
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printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
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printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
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printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
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uintptr_t faultingInstructionAddr = tf->epc;
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uintptr_t faultingInstructionAddr = tf->epc;
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insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr);
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insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr);
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printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);
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printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);
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@ -202,8 +202,8 @@ void handle_misaligned_load(trapframe *tf) {
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}
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}
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void handle_misaligned_store(trapframe *tf) {
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void handle_misaligned_store(trapframe *tf) {
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printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
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printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
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printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
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printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
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uintptr_t faultingInstructionAddr = tf->epc;
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uintptr_t faultingInstructionAddr = tf->epc;
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insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr);
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insn_t faultingInstruction = fetch_instruction(faultingInstructionAddr);
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printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);
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printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);
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