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Enable caching for ROM area in model_6ex/cache_as_ram.inc 

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Sven Schnelle 2011-05-03 07:55:43 +00:00
parent 49ae971333
commit 2f81c03d3a
1 changed files with 11 additions and 1 deletions
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12
src/cpu/intel/model_6ex/cache_as_ram.inc
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@ -201,7 +201,17 @@ clear_mtrrs:
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
movl $0x0000000f, %edx // 36bit address space
wrmsr
/* Enable caching and Speculative Reads for the last 4MB. */
movl $MTRRphysBase_MSR(1), %ecx
movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
movl $0x0000000f, %edx // 36bit address space
wrmsr