From 2f828ebb59fe680ccc6d75793d8c411996130883 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Mon, 12 Feb 2018 12:00:44 +0100 Subject: [PATCH] nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is hopefully more readable. TEST=Build lenovo/x200 with and without this patch (using make BUILD_TIMELESS=1), compare build/coreboot.rom, notice no differences. Change-Id: I079d5353633a3d58ce0e5e616f3fad687a064d65 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/23709 Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/northbridge/intel/gm45/raminit.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index af5faf0caf..08f954d057 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1804,10 +1804,12 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Perform receive-enable calibration. */ raminit_receive_enable_calibration(timings, dimms); /* Lend clock values from receive-enable calibration. */ - MCHBAR32(0x1224) = (MCHBAR32(0x1224) & ~(0xf0)) | - ((((MCHBAR32(0x121c) >> 7) - 1) & 0xf) << 4); - MCHBAR32(0x1324) = (MCHBAR32(0x1324) & ~(0xf0)) | - ((((MCHBAR32(0x131c) >> 7) - 1) & 0xf) << 4); + MCHBAR32(CxDRT5_MCHBAR(0)) = + (MCHBAR32(CxDRT5_MCHBAR(0)) & ~(0xf0)) | + ((((MCHBAR32(CxDRT3_MCHBAR(0)) >> 7) - 1) & 0xf) << 4); + MCHBAR32(CxDRT5_MCHBAR(1)) = + (MCHBAR32(CxDRT5_MCHBAR(1)) & ~(0xf0)) | + ((((MCHBAR32(CxDRT3_MCHBAR(1)) >> 7) - 1) & 0xf) << 4); /* Perform read/write training for high clock rate. */ if (timings->mem_clock == MEM_CLOCK_1067MT) {