soc/mediatek/mt8186: add USB support
1. Enable and setup USB drivers. 2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset the hub via GPIO149. TEST=boot kernel from USB ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -1,9 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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#include <device/device.h>
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#include <soc/usb.h>
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static void mainboard_init(struct device *dev)
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static void mainboard_init(struct device *dev)
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{
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{
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setup_usb_host();
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}
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}
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static void mainboard_enable(struct device *dev)
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static void mainboard_enable(struct device *dev)
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@ -37,6 +37,7 @@ ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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ramstage-y += soc.c
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ramstage-y += soc.c
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ramstage-y += ../common/timer.c timer.c
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ramstage-y += ../common/timer.c timer.c
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ramstage-y += ../common/uart.c
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ramstage-y += ../common/uart.c
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ramstage-y += ../common/usb.c usb.c
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ramstage-y += ../common/wdt.c wdt.c
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ramstage-y += ../common/wdt.c wdt.c
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ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c
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ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6366.c
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@ -64,9 +64,11 @@ enum {
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SPI5_BASE = IO_PHYS + 0x01015000,
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SPI5_BASE = IO_PHYS + 0x01015000,
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I2C5_BASE = IO_PHYS + 0x01016000,
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I2C5_BASE = IO_PHYS + 0x01016000,
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I2C9_BASE = IO_PHYS + 0x01019000,
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I2C9_BASE = IO_PHYS + 0x01019000,
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SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00,
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/* Corsola uses USB2 port1 instead of USB2 port0. */
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SSUSB_IPPC_BASE = IO_PHYS + 0x01283E00,
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MSDC0_BASE = IO_PHYS + 0x01230000,
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MSDC0_BASE = IO_PHYS + 0x01230000,
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SSUSB_SIF_BASE = IO_PHYS + 0x01CA0000,
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/* Corsola uses USB2 port1 instead of USB2 port0. */
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SSUSB_SIF_BASE = IO_PHYS + 0x01C80300,
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EFUSEC_BASE = IO_PHYS + 0x01CB0000,
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EFUSEC_BASE = IO_PHYS + 0x01CB0000,
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MIPITX_BASE = IO_PHYS + 0x01CC0000,
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MIPITX_BASE = IO_PHYS + 0x01CC0000,
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MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000,
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MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000,
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@ -0,0 +1,29 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on MT8186 Functional Specification
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* Chapter number: 5.5
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*/
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#ifndef SOC_MEDIATEK_MT8186_USB_H
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#define SOC_MEDIATEK_MT8186_USB_H
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#include <soc/usb_common.h>
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struct ssusb_sif_port {
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struct sif_u2_phy_com u2phy;
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u32 reserved0[64 * 5];
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struct sif_u3phyd u3phyd;
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u32 reserved1[64];
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struct sif_u3phya u3phya;
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struct sif_u3phya_da u3phya_da;
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u32 reserved2[64 * 3];
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};
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check_member(ssusb_sif_port, u3phyd, 0x600);
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check_member(ssusb_sif_port, u3phya, 0x800);
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check_member(ssusb_sif_port, u3phya_da, 0x900);
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check_member(ssusb_sif_port, reserved2, 0xa00);
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#define USB_PORT_NUMBER 1
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#endif
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@ -0,0 +1,22 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on MT8186 Functional Specification
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* Chapter number: 5.5
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*/
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#include <device/mmio.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <soc/usb.h>
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static void usb3_hub_reset(void)
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{
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gpio_output(GPIO(PERIPHERAL_EN2), 1);
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}
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void mtk_usb_prepare(void)
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{
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usb3_hub_reset();
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gpio_output(GPIO(USB_DRVVBUS_P1), 1);
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}
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