mb/google/brya/var/dochi: Update overridetree
Update overridetree base on schematics revision 20230923. BUG=b:299284564, b:298328847, b:299570339 TEST=emerge-brya coreboot Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78212 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Morris Hsu
Felix Held
parent
d3df99f88d
commit
2fa482d6c5
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@ -495,6 +495,8 @@ config BOARD_GOOGLE_NOKRIS
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config BOARD_GOOGLE_DOCHI
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select SOC_INTEL_RAPTORLAKE
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select DRIVERS_INTEL_ISH
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select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
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if BOARD_GOOGLE_BRYA_COMMON
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@ -5,3 +5,5 @@ romstage-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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ramstage-$(CONFIG_FW_CONFIG) += variant.c
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ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
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@ -0,0 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <console/console.h>
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#include <fw_config.h>
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#include <gpio.h>
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static const struct pad_config fp_disable_pads[] = {
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PAD_NC(GPP_D0, NONE), /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
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PAD_NC(GPP_D1, NONE), /* D1 : ISH_GP1 ==> FP_RST_ODL */
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PAD_NC(GPP_D2, NONE), /* D2 : ISH_GP2 ==> EN_FP_PWR */
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};
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static void fw_config_handle(void *unused)
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{
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if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED))) {
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printk(BIOS_INFO, "Disabling FP pads\n");
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gpio_configure_pads(fp_disable_pads, ARRAY_SIZE(fp_disable_pads));
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
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@ -1,6 +1,370 @@
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fw_config
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field FPMCU_MASK 10
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option FPMCU_DISABLED 0
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option FPMCU_ENABLED 1
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end
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field STORAGE 30 31
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option STORAGE_UNKNOWN 0
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option STORAGE_UFS 1
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option STORAGE_NVME 2
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end
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end
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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# As per Intel Advisory doc#723158, the change is required to prevent possible
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# display flickering issue.
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register "disable_dynamic_tccold_handshake" = "true"
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# SOC Aux orientation override:
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# This is a bitfield that corresponds to up to 4 TCSS ports.
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# Bits (0,1) allocated for TCSS Port1 configuration, Bits (2,3)for TCSS Port2.
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# TcssAuxOri = 0101b
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# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports, otherwise is "0"
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# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
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# motherboard to USBC connector
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register "tcss_aux_ori" = "0x5"
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
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register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
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register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 3
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register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6
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register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3/2 Type A port3
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
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# FIVR configurations are disabled since the board doesn't have V1p05 and Vnn
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# bypass rails implemented.
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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}"
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# Enable the Cnvi BT Audio Offload
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register "cnvi_bt_audio_offload" = "1"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI1 | Fingerprint MCU |
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#| I2C0 | Audio |
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#| I2C1 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C3 | TouchScreen |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 550,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 550,
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.fall_time_ns = 400,
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.data_hold_time_ns = 50,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device ref tbt_pcie_rp0 off end
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device ref tbt_pcie_rp1 off end
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device ref tbt_pcie_rp2 off end
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device ref tcss_dma0 off end
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device ref tcss_dma1 off end
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device ref igpu on
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chip drivers/gfx/generic
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register "device_count" = "6"
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# DDIA for eDP
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register "device[0].name" = ""LCD""
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# DDIB for HDMI
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register "device[1].name" = ""DD01""
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# TCP0 (DP-1) for port C0
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register "device[2].name" = ""DD02""
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register "device[2].use_pld" = "true"
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register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
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register "device[3].name" = ""DD03""
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# TCP2 (DP-3) for port C1
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register "device[4].name" = ""DD04""
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register "device[4].use_pld" = "true"
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register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
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register "device[5].name" = ""DD05""
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device generic 0 on end
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end
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end # Integrated Graphics Device
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DRAM""
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register "options.tsr[1].desc" = ""Soc""
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register "options.tsr[2].desc" = ""Charger""
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# TODO: below values are initial reference values only
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## Active Policy
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(85, 90),
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TEMP_PCT(75, 80),
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TEMP_PCT(68, 70),
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TEMP_PCT(62, 60),
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TEMP_PCT(55, 50),
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TEMP_PCT(50, 40),
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TEMP_PCT(40, 30),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_1,
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.thresholds = {
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TEMP_PCT(60, 90),
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TEMP_PCT(55, 80),
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TEMP_PCT(52, 70),
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TEMP_PCT(48, 60),
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TEMP_PCT(44, 50),
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TEMP_PCT(40, 40),
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TEMP_PCT(36, 30),
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}
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}
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}"
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 18000,
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.max_power = 28000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 40000,
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.max_power = 40000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 6700, 220, 2200, },
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[1] = { 80, 5800, 180, 1800, },
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[2] = { 70, 5000, 145, 1450, },
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[3] = { 60, 4900, 115, 1150, },
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[4] = { 50, 3838, 90, 900, },
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[5] = { 40, 2904, 55, 550, },
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[6] = { 30, 2337, 30, 300, },
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[7] = { 20, 1608, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 alias dptf_policy on end
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end
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end
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device ref pcie4_0 on
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# Enable CPU PCIE RP 1 using CLK 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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probe STORAGE STORAGE_UNKNOWN
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probe STORAGE STORAGE_NVME
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end
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device ref pcie_rp5 off end
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device ref pcie_rp6 off end
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device ref pcie_rp8 off end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5650""
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register "name" = ""RT58""
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register "desc" = ""Realtek RT5650""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-mode""
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register "property_list[0].integer" = "2"
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device i2c 1a on end
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end
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end # I2C0
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device ref i2c1 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
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device i2c 50 on end
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end
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end
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device ref gspi1 on
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chip drivers/spi/acpi
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register "name" = ""CRFP""
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "uid" = "1"
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register "compat_string" = ""google,cros-ec-spi""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
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register "wake" = "GPE0_DW2_15"
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register "has_power_resource" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
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register "enable_delay_ms" = "3"
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device spi 0 on
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probe FPMCU_MASK FPMCU_ENABLED
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end
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end # FPMCU
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end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end
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device ref ish on
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chip drivers/intel/ish
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register "add_acpi_dma_property" = "true"
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device generic 0 on end
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end
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probe STORAGE STORAGE_UNKNOWN
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probe STORAGE STORAGE_UFS
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end
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device ref ufs on
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probe STORAGE STORAGE_UNKNOWN
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probe STORAGE STORAGE_UFS
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port3 as usb2_port
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use tcss_usb3_port3 as usb3_port
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device generic 1 alias conn1 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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register "usb_lpm_incapable" = "true"
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device ref tcss_usb3_port3 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Camera""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0 (DB)""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
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device ref usb2_port9 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port10 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A0 (DB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
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device ref usb3_port1 on end
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end
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end
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end
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end
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end
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end
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|||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <chip.h>
|
||||
#include <fw_config.h>
|
||||
#include <baseboard/variants.h>
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||
{
|
||||
if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED)))
|
||||
config->serial_io_gspi_mode[PchSerialIoIndexGSPI1] = PchSerialIoDisabled;
|
||||
}
|
||||
Loading…
Reference in New Issue