soc/fsp_broadwell_de: Add devhide functionality

Add function to hide IIO PCIe root ports.

TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3]
and make sure OS does not detect built-in NIC.

Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Andrey Petrov 2019-09-10 20:32:56 -07:00 committed by Patrick Georgi
parent 8dc95ddbd4
commit 2fa4938796
5 changed files with 168 additions and 92 deletions

View File

@ -15,6 +15,7 @@ romstage-y += gpio.c
romstage-y += memmap.c
romstage-y += tsc_freq.c
romstage-y += smbus-imc.c
romstage-y += ubox.c
postcar-y += tsc_freq.c
@ -32,6 +33,7 @@ ramstage-y += smi.c
ramstage-y += southcluster.c
ramstage-y += tsc_freq.c
ramstage-y += vtd.c
ramstage-y += ubox.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c

View File

@ -28,6 +28,29 @@
#define SOC_DEVID_ES2 0x6F00
#define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC)
/* DMI2/PCIe link to PCH */
#define PCIE_IIO_PORT_0_DEV 0x00
#define PCIE_IIO_PORT_0_FUNC 0x00
/* IOU2, x8 PCIe Gen3 port */
#define PCIE_IIO_PORT_1_DEV 0x01
#define PCIE_IIO_PORT_1A_FUNC 0x00
#define PCIE_IIO_PORT_1B_FUNC 0x01
/* IOU0: Internal IOSF bridge to 10 GbE and CBDMA */
#define PCIE_IIO_PORT_2_DEV 0x02
#define PCIE_IIO_PORT_2A_FUNC 0x00
#define PCIE_IIO_PORT_2B_FUNC 0x01
#define PCIE_IIO_PORT_2C_FUNC 0x02
#define PCIE_IIO_PORT_2D_FUNC 0x03
/* IOU1: x16 PCIe Gen3 port */
#define PCIE_IIO_PORT_3_DEV 0x03
#define PCIE_IIO_PORT_3A_FUNC 0x00
#define PCIE_IIO_PORT_3B_FUNC 0x01
#define PCIE_IIO_PORT_3C_FUNC 0x02
#define PCIE_IIO_PORT_3D_FUNC 0x03
#define VTD_DEV 5
#define VTD_FUNC 0
#define VTD_DEVID 0x6f28
@ -87,6 +110,7 @@
#define HDA_DEVID 0x8C20
#define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC)
/* Ports from PCH block with adjustable burification settings */
#define PCIE_DEV 28
#define PCIE_PORT1_DEV PCIE_DEV
#define PCIE_PORT1_FUNC 0

View File

@ -27,10 +27,19 @@
#ifndef _BROADWELL_UBOX_H_
#define _BROADWELL_UBOX_H_
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/vtd.h>
#define UBOX_UART_ENABLE 0xf8
#define UBOX_UART_ENABLE_PORT0 (1u << 0)
#define UBOX_UART_ENABLE_PORT1 (1u << 1)
#define UBOX_SC_RESET_STATUS 0xc8
#define UBOX_SC_BYPASS (1u << 3)
#define UBOX_DEVHIDE0 0xb0
void iio_hide(const uint8_t devno, const uint8_t funcno);
#endif

View File

@ -33,6 +33,7 @@
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/acpi.h>
#include <soc/ubox.h>
#include "chip.h"
typedef struct soc_intel_fsp_broadwell_de_config config_t;
@ -250,12 +251,25 @@ void southcluster_enable_dev(struct device *dev)
{
uint32_t reg32;
if (!dev->enabled) {
int slot = PCI_SLOT(dev->path.pci.devfn);
int func = PCI_FUNC(dev->path.pci.devfn);
printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n",
dev_path(dev), slot, func);
if (dev->enabled)
return;
const int slot = PCI_SLOT(dev->path.pci.devfn);
const int func = PCI_FUNC(dev->path.pci.devfn);
switch (slot) {
case PCIE_IIO_PORT_0_DEV:
die("should not hide PCH link");
case PCIE_IIO_PORT_1_DEV: /* fallthrough */
case PCIE_IIO_PORT_2_DEV: /* fallthrough */
case PCIE_IIO_PORT_3_DEV: /* fallthrough */
printk(BIOS_DEBUG, "%s: Disabling IOU bridge %02x.%01x\n", dev_path(dev), slot,
func);
iio_hide(slot, func);
break;
default:
printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot,
func);
/* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);

View File

@ -0,0 +1,27 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Facebook Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <stdint.h>
#include <soc/ubox.h>
void iio_hide(const uint8_t devno, const uint8_t funcno)
{
pci_devfn_t ubox_dev;
ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC);
pci_or_config32(ubox_dev, UBOX_DEVHIDE0 + funcno * 4, 1 << devno);
}