From 2fa8cc35a8e65bfc9d1e1571069fc4d0bad83410 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 15 Jul 2014 02:30:49 +0300 Subject: [PATCH] AGESA hudson: Fix SPI writes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only yangtze has longer FIFO in SPI controller. This was overlooked in commit 9f0a2be AMD SPI: Optimise for longer writes which broke SPI writes and caused CBFS errors with fam15tn. Change-Id: I821e3f1fa186d2383b30eab9c5d52797c2ef22c5 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/6273 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering --- src/southbridge/amd/agesa/hudson/Kconfig | 5 ----- src/southbridge/amd/agesa/hudson/spi.c | 4 ++++ 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index a0c68a323d..9652a8dcf8 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -224,11 +224,6 @@ config HUDSON_LEGACY_FREE endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE if SOUTHBRIDGE_AMD_AGESA_YANGTZE - config AMD_SB_SPI_TX_LEN - int - default 64 - depends on SPI_FLASH - config AZ_PIN hex default 0xaa diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 2aeb2c04c0..bbf6dd3ee2 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -43,7 +43,11 @@ static int bus_claimed = 0; #define SPI_REG_CNTRL11 0xd #define CNTRL11_FIFOPTR_MASK 0x07 +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define AMD_SB_SPI_TX_LEN 64 +#else +#define AMD_SB_SPI_TX_LEN 8 +#endif static u32 spibar;