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AGESA Hudson/Yangtze: Remove unused GPP configuration in devicetree 

GPP config from devicetree.cb is not implemented for fam15tn/fam16kb.

Also only for asus/f2a85-m the configuration value matched the actual
programming.

Change-Id: Ic7a9aa1360f4ba35d202f3f7dd1fc3c20a52dde0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7600
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Kyösti Mälkki 2014-11-21 08:40:55 +02:00
parent 7d8cde756e
commit 2fd006a3e3
7 changed files with 0 additions and 7 deletions
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1
src/mainboard/amd/parmer/devicetree.cb
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@ -68,7 +68,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 15.1 off end # PCIe 1
device pci 15.2 off end # PCIe 2
device pci 15.3 off end # PCIe 3
register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson
device pci 18.0 on end

1
src/mainboard/amd/thatcher/devicetree.cb
View File

@ -83,7 +83,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 15.1 off end # PCIe 1
device pci 15.2 off end # PCIe 2
device pci 15.3 off end # PCIe 3
register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson
device pci 18.0 on end

1
src/mainboard/asus/f2a85-m/devicetree.cb
View File

@ -116,7 +116,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 15.2 off end # unused
device pci 15.3 off end # unused
register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson
device pci 18.0 on end

1
src/mainboard/asus/f2a85-m_le/devicetree.cb
View File

@ -115,7 +115,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 15.1 on end # PCIe 1 onboard gigabit
device pci 15.2 off end # unused
device pci 15.3 off end # unused
register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson
device pci 18.0 on end

1
src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb
View File

@ -68,7 +68,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 15.1 off end # PCIe 1
device pci 15.2 off end # PCIe 2
device pci 15.3 off end # PCIe 3
register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson
device pci 18.0 on end

1
src/mainboard/lenovo/g505s/devicetree.cb
View File

@ -72,7 +72,6 @@ chip northbridge/amd/agesa/family15rl/root_complex
device pci 15.1 off end # PCIe 1
device pci 15.2 off end # PCIe 2
device pci 15.3 off end # PCIe 3
register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson
device pci 18.0 on end

1
src/southbridge/amd/agesa/hudson/chip.h
View File

@ -22,7 +22,6 @@
struct southbridge_amd_agesa_hudson_config
{
u8 gpp_configuration;
u8 sd_mode;
};