mb/intel/icelake_rvp: Configure eSPI IO decode range for EC
This implementation adds eSPI IO decode range for EC. 1. 0x800-0x8FF / 0x200-020F: EC host command range. 2. 0x900-0x9ff: EC memory map range. Change-Id: I69e6b3a83c072036c5b3ae801f8d80dfda82478e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/29764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
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@ -27,6 +27,12 @@ chip soc/intel/icelake
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "PchHdaDspEnable" = "1"
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register "PchHdaDspEnable" = "1"
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register "PchHdaAudioLinkHda" = "1"
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register "PchHdaAudioLinkHda" = "1"
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@ -27,6 +27,12 @@ chip soc/intel/icelake
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "PchHdaDspEnable" = "1"
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register "PchHdaDspEnable" = "1"
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register "PchHdaAudioLinkHda" = "1"
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register "PchHdaAudioLinkHda" = "1"
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register "PchHdaAudioLinkSsp0" = "1"
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register "PchHdaAudioLinkSsp0" = "1"
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