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mb/intel/icelake_rvp: Configure eSPI IO decode range for EC 

This implementation adds eSPI IO decode range for EC.
1. 0x800-0x8FF / 0x200-020F: EC host command range.
2. 0x900-0x9ff: EC memory map range.

Change-Id: I69e6b3a83c072036c5b3ae801f8d80dfda82478e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Aamir Bohra 2018-11-21 11:08:04 +05:30 committed by Subrata Banik
parent bbf1df76a6
commit 2fd2923aeb
2 changed files with 12 additions and 0 deletions
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6
src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
View File

@ -27,6 +27,12 @@ chip soc/intel/icelake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHda" = "1"

6
src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
View File

@ -27,6 +27,12 @@ chip soc/intel/icelake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHda" = "1"
register "PchHdaAudioLinkSsp0" = "1"